I had not understood how MSIs work and I was unnecessarily routing them
through IOAPIC. This is not necessary and should not be done :D
Also MSIs were reserving interrupts that IOAPIC was capable of
generating. Now IOAPIC and MSIs use different set of interrupts so
IOAPIC can use more interrupts if needed.
Before I assumed that bootloaders loaded the kernel at physical address
0, but this patch kinda allows loading to different addresses. This
still doesn't fully work as kernel bootstrap paging relies on kernel
being loaded at 0
Node now have APIs to convert them to buffer, integer and string. This
allows possibility to handle methods that need explicitly use one of the
overloads instead of integer.
This patch also adds handling of DebugOp. This is used quite heavily in
uACPIs test suite.
Change Semaphore -> ThreadBlocker
This was not a semaphore, I just named it one because I didn't know
what semaphore was. I have meant to change this sooner, but it was in
no way urgent :D
Implement SMP events. Processors can now be sent SMP events through
IPIs. SMP events can be sent either to a single processor or broadcasted
to every processor.
PageTable::{map_page,map_range,unmap_page,unmap_range}() now send SMP
event to invalidate TLB caches for the changed pages.
Scheduler no longer uses a global run queue. Each processor has its own
scheduler that keeps track of the load on the processor. Once every
second schedulers do load balancing. Schedulers have no access to other
processors' schedulers, they just see approximate loads. If scheduler
decides that it has too much load, it will send a thread to another
processor through a SMP event.
Schedulers are currently run using the timer interrupt on BSB. This
should be not the case, and each processor should use its LAPIC timer
for interrupts. There is no reason to broadcast SMP event to all
processors when BSB gets timer interrupt.
Old scheduler only achieved 20% idle load on qemu. That was probably a
very inefficient implementation. This new scheduler seems to average
around 1% idle load. This is much closer to what I would expect. On my
own laptop idle load seems to be only around 0.5% on each processor.
Only segment 0 is supported, but devices can now be accessed through
mmio.
Adding more segments would require adding argument to every PCI API so
it is left for later.
Remove tree-like structure from AML. This allows more spec compliant
parsing of named objects inside not yet declared devices.
This also allows AML to be run thread safely. All object adds/removes
are now guarded by a mutex.
This patch implements basic support for power button using ACPI
fixed events. I still need to implement general purpose events
and embedded controller for full power button support.
Now global lock uses the actual global lock. Currenly if no lock
can be acquired, we just panic the kernel so that I remember to
implement it properly once AML is running concurrently.
I had forgotten that Processors used to be a different definition
in AML.
I also implemented reads/writes for FieldElement/IndexFieldElement
that fit in 64 bits. Reads and writes to buffer are still a TODO.
Method invocation is starting to come together. This implemenetation
can interpret some of the qemu's functions to enter ACPI mode.
PCI config space access is currently the one thing is between
entering ACPI mode.
Now AML parsing is actually done while respecting namespaces and
scopes. I implemented the minimal functionality to parse qemu's AML.
Next step is to implement AML interpreting and then we can drop lai
as a dependency.
This implements only parsing for AML in qemu. InvokeMethods are not
parsed since number of arguments to Methods is not yet known.
Parsing AML uses multiple kilobytes of stack space, so I increased
boot stack size by a lot :D
I am not sure where my own AML is going, but this is good start if
I decide to implement full ACPI on my own.
This code is very much just ugly macro expansion.
Qemu has 2 DefPackage elements that I am not able to parse. Package
data ends while there should be still multiple elements.