Commit Graph

15 Commits

Author SHA1 Message Date
Bananymous 539afb329a Kernel: All processors use LAPIC timer when running with APIC
This makes scheduler preemption much cleaner as bsb does not have to
send smp messages to notify other processes about timer interrupt.

Also PIT percision is now "full" 0.8 us instead of 1 ms that I was using
before.
2024-07-23 02:28:52 +03:00
Bananymous f8261c60c0 Kernel: Rewrite the whole scheduler and re-architecture SMP handling
Change Semaphore -> ThreadBlocker
  This was not a semaphore, I just named it one because I didn't know
  what semaphore was. I have meant to change this sooner, but it was in
  no way urgent :D

Implement SMP events. Processors can now be sent SMP events through
IPIs. SMP events can be sent either to a single processor or broadcasted
to every processor.

PageTable::{map_page,map_range,unmap_page,unmap_range}() now send SMP
event to invalidate TLB caches for the changed pages.

Scheduler no longer uses a global run queue. Each processor has its own
scheduler that keeps track of the load on the processor. Once every
second schedulers do load balancing. Schedulers have no access to other
processors' schedulers, they just see approximate loads. If scheduler
decides that it has too much load, it will send a thread to another
processor through a SMP event.

Schedulers are currently run using the timer interrupt on BSB. This
should be not the case, and each processor should use its LAPIC timer
for interrupts. There is no reason to broadcast SMP event to all
processors when BSB gets timer interrupt.

Old scheduler only achieved 20% idle load on qemu. That was probably a
very inefficient implementation. This new scheduler seems to average
around 1% idle load. This is much closer to what I would expect. On my
own laptop idle load seems to be only around 0.5% on each processor.
2024-07-22 00:33:50 +03:00
Bananymous f8c01418b1 Kernel: Fix multiprocessing on x86_64
I did not even start APs after initializing them... :D
2024-04-03 14:21:55 +03:00
Bananymous 5050047cef Kernel: Rewrite whole scheduler
Current context saving was very hacky and dependant on compiler
behaviour that was not consistent. Now we always use iret for
context saving. This makes everything more clean.
2024-03-29 18:02:12 +02:00
Bananymous d7bf34ecd0 Kernel: Write isr handler for x86_32 and cleanup x86_64 2024-03-26 20:16:20 +02:00
Bananymous 89ca4c8a8b Kernel: Implement IPI broadcasting 2024-03-09 23:53:38 +02:00
Bananymous dfe5a2d665 All: Cleanup all files
Add newline to end of files and remove whitespace from end of lines
2024-01-24 15:53:38 +02:00
Bananymous 518fd3fad0 Kernel: Add 16 more irq handlers
IDT will now panic if trying to assing handler for non supported
irq.
2023-10-13 16:17:27 +03:00
Bananymous 9729e5a05b Kernel: Change signal kernel API
return rsp and rip are now stored per thread
2023-07-23 18:33:10 +03:00
Bananymous 4e35b8b49d Kernel: Syscalls now get the interrupt stack 2023-07-21 11:04:16 +03:00
Bananymous ff2e2937a5 Kernel: Remove offset from OpenFileDescriptor
This is now handled on the libc side. There might be reasons to
have it in kernel side, but for simplicity's sake I'm moving it
to libc for now :)
2023-05-09 20:31:22 +03:00
Bananymous fc71d2f7c4 Kernel: Don't call 'cli' on interrupt
This is automatically done because we are using interrupt gates
in the IDT
2023-04-21 11:18:08 +03:00
Bananymous 8b8e3cbbf0 Kernel/Userspace: Start initial work on userspace and syscalls 2023-03-13 15:32:46 +02:00
Bananymous 6dc22b7251 Kernel: Add actual register values to x86_64 kernel panic
Very hackish implementation, but we now get actual registers at the
time of the interrupt happening
2023-01-30 18:52:38 +02:00
Bananymous b315fdc27f Kernel: Finally managed to get 64-bit working
I had weird problems with interrupts but everything should work now
2023-01-25 19:19:28 +02:00