banan-os/kernel/arch/x86_64/interrupts.S

.macro pushaq
	pushq %rax
	pushq %rcx
	pushq %rdx
	pushq %rbx
	pushq %rbp
	pushq %rsi
	pushq %rdi
	pushq %r8
	pushq %r9
	pushq %r10
	pushq %r11
	pushq %r12
	pushq %r13
	pushq %r14
	pushq %r15
.endm

.macro popaq
	popq %r15
	popq %r14
	popq %r13
	popq %r12
	popq %r11
	popq %r10
	popq %r9
	popq %r8
	popq %rdi
	popq %rsi
	popq %rbp
	popq %rbx
	popq %rdx
	popq %rcx
	popq %rax
.endm

isr_stub:
	pushaq

	movq %cr0, %rax; pushq %rax
	movq %cr2, %rax; pushq %rax
	movq %cr3, %rax; pushq %rax
	movq %cr4, %rax; pushq %rax

	movq 152(%rsp), %rdi	// isr number
	movq 160(%rsp), %rsi	// error code
	leaq 168(%rsp), %rdx	// interrupt stack ptr
	movq %rsp, %rcx			// register ptr
	call cpp_isr_handler
	addq $32, %rsp

	popaq
	addq $16, %rsp
	iretq

irq_stub:
	pushaq
	movq 120(%rsp), %rdi	# irq number
	call cpp_irq_handler
	popaq
	addq $16, %rsp
	iretq

.global asm_yield_handler
asm_yield_handler:
	pushaq
	leaq 120(%rsp), %rdi # interrupt stack ptr
	movq     %rsp,  %rsi # interrupt register ptr
	call cpp_yield_handler
	popaq
	iretq

.global asm_ipi_handler
asm_ipi_handler:
	pushaq
	call cpp_ipi_handler
	popaq
	iretq

.global asm_timer_handler
asm_timer_handler:
	pushaq
	call cpp_timer_handler
	popaq
	iretq

.macro isr n
	.global isr\n
	isr\n:
		pushq $0
		pushq $\n
		jmp isr_stub
.endm

.macro isr_err n
	.global isr\n
	isr\n:
		pushq $\n
		jmp isr_stub
.endm

.macro irq n
	.global irq\n
	irq\n:
		pushq $0
		pushq $\n
		jmp irq_stub
.endm

isr 0
isr 1
isr 2
isr 3
isr 4
isr 5
isr 6
isr 7
isr_err 8
isr 9
isr_err 10
isr_err 11
isr_err 12
isr_err 13
isr_err 14
isr 15
isr 16
isr_err 17
isr 18
isr 19
isr 20
isr 21
isr 22
isr 23
isr 24
isr 25
isr 26
isr 27
isr 28
isr 29
isr 30
isr 31

irq 0
irq 1
irq 2
irq 3
irq 4
irq 5
irq 6
irq 7
irq 8
irq 9
irq 10
irq 11
irq 12
irq 13
irq 14
irq 15
irq 16
irq 17
irq 18
irq 19
irq 20
irq 21
irq 22
irq 23
irq 24
irq 25
irq 26
irq 27
irq 28
irq 29
irq 30
irq 31
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now 2023-01-25 19:05:47 +02:00			`.macro pushaq`
			`pushq %rax`
			`pushq %rcx`
			`pushq %rdx`
Kernel: Write isr handler for x86_32 and cleanup x86_64 2024-03-26 16:36:51 +02:00			`pushq %rbx`
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now 2023-01-25 19:05:47 +02:00			`pushq %rbp`
			`pushq %rsi`
Kernel: Write isr handler for x86_32 and cleanup x86_64 2024-03-26 16:36:51 +02:00			`pushq %rdi`
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now 2023-01-25 19:05:47 +02:00			`pushq %r8`
			`pushq %r9`
			`pushq %r10`
			`pushq %r11`
			`pushq %r12`
			`pushq %r13`
			`pushq %r14`
			`pushq %r15`
			`.endm`

			`.macro popaq`
			`popq %r15`
			`popq %r14`
			`popq %r13`
			`popq %r12`
			`popq %r11`
			`popq %r10`
			`popq %r9`
			`popq %r8`
			`popq %rdi`
Kernel: Write isr handler for x86_32 and cleanup x86_64 2024-03-26 16:36:51 +02:00			`popq %rsi`
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now 2023-01-25 19:05:47 +02:00			`popq %rbp`
Kernel: Write isr handler for x86_32 and cleanup x86_64 2024-03-26 16:36:51 +02:00			`popq %rbx`
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now 2023-01-25 19:05:47 +02:00			`popq %rdx`
			`popq %rcx`
			`popq %rax`
			`.endm`

			`isr_stub:`
			`pushaq`
Kernel: Add actual register values to x86_64 kernel panic Very hackish implementation, but we now get actual registers at the time of the interrupt happening 2023-01-30 18:52:38 +02:00
Kernel: Write isr handler for x86_32 and cleanup x86_64 2024-03-26 16:36:51 +02:00			`movq %cr0, %rax; pushq %rax`
			`movq %cr2, %rax; pushq %rax`
			`movq %cr3, %rax; pushq %rax`
			`movq %cr4, %rax; pushq %rax`
Kernel: Add actual register values to x86_64 kernel panic Very hackish implementation, but we now get actual registers at the time of the interrupt happening 2023-01-30 18:52:38 +02:00
Kernel: Write isr handler for x86_32 and cleanup x86_64 2024-03-26 16:36:51 +02:00			`movq 152(%rsp), %rdi // isr number`
			`movq 160(%rsp), %rsi // error code`
			`leaq 168(%rsp), %rdx // interrupt stack ptr`
			`movq %rsp, %rcx // register ptr`
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now 2023-01-25 19:05:47 +02:00			`call cpp_isr_handler`
Kernel: Write isr handler for x86_32 and cleanup x86_64 2024-03-26 16:36:51 +02:00			`addq $32, %rsp`

Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now 2023-01-25 19:05:47 +02:00			`popaq`
			`addq $16, %rsp`
			`iretq`

			`irq_stub:`
			`pushaq`
Kernel: Rewrite whole scheduler Current context saving was very hacky and dependant on compiler behaviour that was not consistent. Now we always use iret for context saving. This makes everything more clean. 2024-03-29 18:02:12 +02:00			`movq 120(%rsp), %rdi # irq number`
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now 2023-01-25 19:05:47 +02:00			`call cpp_irq_handler`
			`popaq`
			`addq $16, %rsp`
			`iretq`

Kernel: Fix multiprocessing on x86_64 I did not even start APs after initializing them... :D 2024-04-03 14:21:55 +03:00			`.global asm_yield_handler`
			`asm_yield_handler:`
			`pushaq`
			`leaq 120(%rsp), %rdi # interrupt stack ptr`
			`movq %rsp, %rsi # interrupt register ptr`
			`call cpp_yield_handler`
			`popaq`
			`iretq`

Kernel: Rewrite the whole scheduler and re-architecture SMP handling Change Semaphore -> ThreadBlocker This was not a semaphore, I just named it one because I didn't know what semaphore was. I have meant to change this sooner, but it was in no way urgent :D Implement SMP events. Processors can now be sent SMP events through IPIs. SMP events can be sent either to a single processor or broadcasted to every processor. PageTable::{map_page,map_range,unmap_page,unmap_range}() now send SMP event to invalidate TLB caches for the changed pages. Scheduler no longer uses a global run queue. Each processor has its own scheduler that keeps track of the load on the processor. Once every second schedulers do load balancing. Schedulers have no access to other processors' schedulers, they just see approximate loads. If scheduler decides that it has too much load, it will send a thread to another processor through a SMP event. Schedulers are currently run using the timer interrupt on BSB. This should be not the case, and each processor should use its LAPIC timer for interrupts. There is no reason to broadcast SMP event to all processors when BSB gets timer interrupt. Old scheduler only achieved 20% idle load on qemu. That was probably a very inefficient implementation. This new scheduler seems to average around 1% idle load. This is much closer to what I would expect. On my own laptop idle load seems to be only around 0.5% on each processor. 2024-07-22 00:33:50 +03:00			`.global asm_ipi_handler`
			`asm_ipi_handler:`
			`pushaq`
			`call cpp_ipi_handler`
			`popaq`
			`iretq`

Kernel: All processors use LAPIC timer when running with APIC This makes scheduler preemption much cleaner as bsb does not have to send smp messages to notify other processes about timer interrupt. Also PIT percision is now "full" 0.8 us instead of 1 ms that I was using before. 2024-07-23 02:28:52 +03:00			`.global asm_timer_handler`
			`asm_timer_handler:`
			`pushaq`
			`call cpp_timer_handler`
			`popaq`
			`iretq`

Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now 2023-01-25 19:05:47 +02:00			`.macro isr n`
			`.global isr\n`
			`isr\n:`
			`pushq $0`
			`pushq $\n`
			`jmp isr_stub`
			`.endm`

			`.macro isr_err n`
			`.global isr\n`
			`isr\n:`
			`pushq $\n`
			`jmp isr_stub`
			`.endm`

			`.macro irq n`
			`.global irq\n`
			`irq\n:`
			`pushq $0`
			`pushq $\n`
			`jmp irq_stub`
			`.endm`

			`isr 0`
			`isr 1`
			`isr 2`
			`isr 3`
			`isr 4`
			`isr 5`
			`isr 6`
			`isr 7`
			`isr_err 8`
			`isr 9`
			`isr_err 10`
			`isr_err 11`
			`isr_err 12`
			`isr_err 13`
			`isr_err 14`
			`isr 15`
			`isr 16`
			`isr_err 17`
			`isr 18`
			`isr 19`
			`isr 20`
			`isr 21`
			`isr 22`
			`isr 23`
			`isr 24`
			`isr 25`
			`isr 26`
			`isr 27`
			`isr 28`
			`isr 29`
			`isr 30`
			`isr 31`

			`irq 0`
			`irq 1`
			`irq 2`
			`irq 3`
			`irq 4`
			`irq 5`
			`irq 6`
			`irq 7`
			`irq 8`
			`irq 9`
			`irq 10`
			`irq 11`
			`irq 12`
			`irq 13`
			`irq 14`
			`irq 15`
Kernel: Add 16 more irq handlers IDT will now panic if trying to assing handler for non supported irq. 2023-10-13 14:11:23 +03:00			`irq 16`
			`irq 17`
			`irq 18`
			`irq 19`
			`irq 20`
			`irq 21`
			`irq 22`
			`irq 23`
			`irq 24`
			`irq 25`
			`irq 26`
			`irq 27`
			`irq 28`
			`irq 29`
			`irq 30`
			`irq 31`