Commit Graph

9 Commits

Author SHA1 Message Date
Bananymous 539afb329a Kernel: All processors use LAPIC timer when running with APIC
This makes scheduler preemption much cleaner as bsb does not have to
send smp messages to notify other processes about timer interrupt.

Also PIT percision is now "full" 0.8 us instead of 1 ms that I was using
before.
2024-07-23 02:28:52 +03:00
Bananymous f8261c60c0 Kernel: Rewrite the whole scheduler and re-architecture SMP handling
Change Semaphore -> ThreadBlocker
  This was not a semaphore, I just named it one because I didn't know
  what semaphore was. I have meant to change this sooner, but it was in
  no way urgent :D

Implement SMP events. Processors can now be sent SMP events through
IPIs. SMP events can be sent either to a single processor or broadcasted
to every processor.

PageTable::{map_page,map_range,unmap_page,unmap_range}() now send SMP
event to invalidate TLB caches for the changed pages.

Scheduler no longer uses a global run queue. Each processor has its own
scheduler that keeps track of the load on the processor. Once every
second schedulers do load balancing. Schedulers have no access to other
processors' schedulers, they just see approximate loads. If scheduler
decides that it has too much load, it will send a thread to another
processor through a SMP event.

Schedulers are currently run using the timer interrupt on BSB. This
should be not the case, and each processor should use its LAPIC timer
for interrupts. There is no reason to broadcast SMP event to all
processors when BSB gets timer interrupt.

Old scheduler only achieved 20% idle load on qemu. That was probably a
very inefficient implementation. This new scheduler seems to average
around 1% idle load. This is much closer to what I would expect. On my
own laptop idle load seems to be only around 0.5% on each processor.
2024-07-22 00:33:50 +03:00
Bananymous 1ee37cb671 Kernel: Make sure stack is aligned on interrupts for i686 target
I just realized that only x86_64 aligns stack pointer when interrupt is
triggered.
2024-07-22 00:10:42 +03:00
Bananymous 7ef751ba95 Kernel: Fix multiprocessor for i686
i686 is now actually ran with multiple processors.
2024-04-03 14:42:17 +03:00
Bananymous 0dd74e3c9d Kernel: Implement syscalls for i686 and cleanup x86_64
This actually allows i686 to boot properly!
2024-04-03 02:23:23 +03:00
Bananymous 4d70322eab Kernel: Save segment registers on all interrupts on i686 2024-04-03 00:41:13 +03:00
Bananymous 2106a9e373 Kernel: Rework scheduler/processor stacks. 2024-04-02 12:34:42 +03:00
Bananymous d7bf34ecd0 Kernel: Write isr handler for x86_32 and cleanup x86_64 2024-03-26 20:16:20 +02:00
Bananymous 1943c3e7a1 Kernel: Unify IDT and GDT code between x86_64 and x86_32
The code is pretty much the same, so there are just couple macros
differiating initialization.
2024-03-26 16:42:02 +02:00