USB device now sets its own data buffers for IN/OUT endpoints. This
allows more customization and parallelism as data buffer does not have
to be shared.
I thought that I had an PC without LBA support so I implement support
for CHS. Turns out that my ATA device detection was broken and was no
device on that port and initialize data was just garbage.
Now that I added CHS, I guess I should just keep it in :)
Both ATA read and write are now combined into a single function to avoid
code duplication.
kernel now passes the name of default console to init process so init
knows which file to open as stdio. before /dev/tty was referencing the
system wide current terminal which was inherited from cmdline. This
doesn't work anymore as we have pseudo terminals implemented that can
chage the current terminal during runtime :D
Quake II needs a lot of stack, it was overflowing my 256 KiB stack so
this patch doubles that, so Quake II can run!
Also every thread had 256 KiB kernel stack. This is unnecessarily large
and now dropped to 32 KiB.
SSE is now unconditionally enabled any where and most of math.h is now
actually implemented. using __builtin_<func> lead to many hangs where
the builtin function would just call itself.
I had not understood how MSIs work and I was unnecessarily routing them
through IOAPIC. This is not necessary and should not be done :D
Also MSIs were reserving interrupts that IOAPIC was capable of
generating. Now IOAPIC and MSIs use different set of interrupts so
IOAPIC can use more interrupts if needed.
This patch builds new executable image to another pml4 structure and
only after everything is validated will current context be replaced.
This allows exec to fail "late" where previously it would panic the
kernel or kill the process. This allows graceful handling of exec
failures in userspace!
HPET supports reading LAPIC counter without locks, so it can be done in
parallel. This makes booting much faster. Previously initializing every
timer took 100 ms, so 16 CPUs took total of 1.6 seconds. This allows
doing it all in 100 ms.
ELFs are now loaded as MemoryRegions so they don't need special handling
anywhere. This also allows file backed COW optimizations to work. This
was not the case before.
This patch removes now obsolete LoadableELF and unused ELF files from
LibElf.
Before I assumed that bootloaders loaded the kernel at physical address
0, but this patch kinda allows loading to different addresses. This
still doesn't fully work as kernel bootstrap paging relies on kernel
being loaded at 0
Node now have APIs to convert them to buffer, integer and string. This
allows possibility to handle methods that need explicitly use one of the
overloads instead of integer.
This patch also adds handling of DebugOp. This is used quite heavily in
uACPIs test suite.
This patch implements posix_openpt() and ptsname()
grantpt() and unlockpt() are left in LibC as stubs, as posix_openpt
currently does all of the needed work.
This makes scheduler preemption much cleaner as bsb does not have to
send smp messages to notify other processes about timer interrupt.
Also PIT percision is now "full" 0.8 us instead of 1 ms that I was using
before.
Change Semaphore -> ThreadBlocker
This was not a semaphore, I just named it one because I didn't know
what semaphore was. I have meant to change this sooner, but it was in
no way urgent :D
Implement SMP events. Processors can now be sent SMP events through
IPIs. SMP events can be sent either to a single processor or broadcasted
to every processor.
PageTable::{map_page,map_range,unmap_page,unmap_range}() now send SMP
event to invalidate TLB caches for the changed pages.
Scheduler no longer uses a global run queue. Each processor has its own
scheduler that keeps track of the load on the processor. Once every
second schedulers do load balancing. Schedulers have no access to other
processors' schedulers, they just see approximate loads. If scheduler
decides that it has too much load, it will send a thread to another
processor through a SMP event.
Schedulers are currently run using the timer interrupt on BSB. This
should be not the case, and each processor should use its LAPIC timer
for interrupts. There is no reason to broadcast SMP event to all
processors when BSB gets timer interrupt.
Old scheduler only achieved 20% idle load on qemu. That was probably a
very inefficient implementation. This new scheduler seems to average
around 1% idle load. This is much closer to what I would expect. On my
own laptop idle load seems to be only around 0.5% on each processor.
Bananymous