I was polling the wrong bit in read/write which lead to dead locks on
machines that used embedded controllers :D
Also EC GPEs are now only initialized AFTER the ACPI post initialization
is done. This fixes some issues where _GPE body was not fully available
yet
Now modifying Scheduler.h or Thread.h doesnt trigger practically a full
kernel rebuild. This required moving Mutex and RWLock of of line but
that should be fine :^)
There is no need to pass the current mode as an argument as ACPI has
access to that info either way.
Only route INTx objects when using ACPI, they won't be used otherwise
The old SpinLockAsMutex was pretty confusing first of all. It also was
causing the issue thats been around for maybe a year now which is the
only consistently happening kernel panic. I've been pretty confused
about this and finally figured out what was causing this.
The main issue was that we were accidentally enabling interrupts when
blocking a thread that passed SpinLockAsMutex from normally interrupt
enabled context. This led to receiving IPI for thread unblock while
we were actively blocking the thread. I'm very suprized this had't
caused any more serious issues than occasional kernel panics :^)
Kernel can just use raw threads, pretty muchs the only thing that
process provides is syscalls which kernel threads of course don't
need.
Also this makes init process have pid 1 :D
All block functions now take an optional mutex parameter that is
atomically unlocked instead of having the user unlock it before hand.
This prevents a ton of race conditions everywhere in the code!
Now _REG, _STA, _INI are called in the order my laptop expects them to
be called. This was kinda weird because what uACPI was doing did not
work.
\_SB_.PCI0.LPC0.EC0_.BAT0._STA required \_SB_.PCI0.LPC0.EC0_._REG to be
called
\_SB_.PCI0.LPC0.EC0_._REG required \_SB_.PCI0._STA to be called
Now I call all the _REG methods of a device after calling _STA/_INI and
after performing the whole _STA/_INI sequence i call rest of missing
_REG functions
The old AML interpreter was trash and did not follow value/reference
semantics at all. It was also super slow, one of my machines taking over
7 seconds to parse ACPI namespace and call _INI and _STA.
I had not understood how MSIs work and I was unnecessarily routing them
through IOAPIC. This is not necessary and should not be done :D
Also MSIs were reserving interrupts that IOAPIC was capable of
generating. Now IOAPIC and MSIs use different set of interrupts so
IOAPIC can use more interrupts if needed.
Before I assumed that bootloaders loaded the kernel at physical address
0, but this patch kinda allows loading to different addresses. This
still doesn't fully work as kernel bootstrap paging relies on kernel
being loaded at 0
Node now have APIs to convert them to buffer, integer and string. This
allows possibility to handle methods that need explicitly use one of the
overloads instead of integer.
This patch also adds handling of DebugOp. This is used quite heavily in
uACPIs test suite.
Change Semaphore -> ThreadBlocker
This was not a semaphore, I just named it one because I didn't know
what semaphore was. I have meant to change this sooner, but it was in
no way urgent :D
Implement SMP events. Processors can now be sent SMP events through
IPIs. SMP events can be sent either to a single processor or broadcasted
to every processor.
PageTable::{map_page,map_range,unmap_page,unmap_range}() now send SMP
event to invalidate TLB caches for the changed pages.
Scheduler no longer uses a global run queue. Each processor has its own
scheduler that keeps track of the load on the processor. Once every
second schedulers do load balancing. Schedulers have no access to other
processors' schedulers, they just see approximate loads. If scheduler
decides that it has too much load, it will send a thread to another
processor through a SMP event.
Schedulers are currently run using the timer interrupt on BSB. This
should be not the case, and each processor should use its LAPIC timer
for interrupts. There is no reason to broadcast SMP event to all
processors when BSB gets timer interrupt.
Old scheduler only achieved 20% idle load on qemu. That was probably a
very inefficient implementation. This new scheduler seems to average
around 1% idle load. This is much closer to what I would expect. On my
own laptop idle load seems to be only around 0.5% on each processor.
This patch implements basic support for power button using ACPI
fixed events. I still need to implement general purpose events
and embedded controller for full power button support.
Now global lock uses the actual global lock. Currenly if no lock
can be acquired, we just panic the kernel so that I remember to
implement it properly once AML is running concurrently.
I had forgotten that Processors used to be a different definition
in AML.
I also implemented reads/writes for FieldElement/IndexFieldElement
that fit in 64 bits. Reads and writes to buffer are still a TODO.
Method invocation is starting to come together. This implemenetation
can interpret some of the qemu's functions to enter ACPI mode.
PCI config space access is currently the one thing is between
entering ACPI mode.
Now AML parsing is actually done while respecting namespaces and
scopes. I implemented the minimal functionality to parse qemu's AML.
Next step is to implement AML interpreting and then we can drop lai
as a dependency.
Bananymous