233 lines
4.4 KiB
C++
233 lines
4.4 KiB
C++
#pragma once
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#include <stdint.h>
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namespace Kernel
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{
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enum E1000_REG : uint32_t
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{
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REG_CTRL = 0x0000,
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REG_STATUS = 0x0008,
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REG_EERD = 0x0014,
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REG_ICR = 0x00C0,
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REG_ITR = 0x00C4,
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REG_IMS = 0x00D0,
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REG_IMC = 0x00D8,
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REG_IVAR = 0x00E4,
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REG_EITR = 0x00E8,
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REG_RCTL = 0x0100,
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REG_TCTL = 0x0400,
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REG_TIPG = 0x0410,
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REG_RDBAL0 = 0x2800,
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REG_RDBAH0 = 0x2804,
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REG_RDLEN0 = 0x2808,
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REG_RDH0 = 0x2810,
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REG_RDT0 = 0x2818,
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REG_TDBAL = 0x3800,
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REG_TDBAH = 0x3804,
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REG_TDLEN = 0x3808,
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REG_TDH = 0x3810,
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REG_TDT = 0x3818,
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REG_RXCSUM = 0x5000,
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REG_MTA = 0x5200,
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};
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enum E1000_CTRL : uint32_t
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{
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CTRL_FD = 1u << 0,
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CTRL_GIOMD = 1u << 2,
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CTRL_ASDE = 1u << 5,
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CTRL_SLU = 1u << 6,
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CTRL_FRCSPD = 1u << 11,
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CTRL_FCRDBLX = 1u << 12,
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CTRL_ADVD3WUC = 1u << 20,
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CTRL_RST = 1u << 26,
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CTRL_RFCE = 1u << 27,
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CTRL_TFCE = 1u << 28,
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CTRL_VME = 1u << 30,
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CTRL_PHY_RST = 1u << 31,
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CTRL_SPEED_10MB = 0b00 << 8,
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CTRL_SPEED_100MB = 0b01 << 8,
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CTRL_SPEED_1000MB1 = 0b10 << 8,
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CTRL_SPEED_1000MB2 = 0b11 << 8,
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};
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enum E1000_STATUS : uint32_t
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{
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STATUS_LU = 1 << 1,
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STATUS_SPEED_MASK = 0b11 << 6,
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STATUS_SPEED_10MB = 0b00 << 6,
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STATUS_SPEED_100MB = 0b01 << 6,
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STATUS_SPEED_1000MB1 = 0b10 << 6,
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STATUS_SPEED_1000MB2 = 0b11 << 6,
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};
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enum E1000_ICR : uint32_t
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{
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ICR_TXDW = 1 << 0,
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ICR_TXQE = 1 << 1,
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ICR_LSC = 1 << 2,
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ICR_RXDMT0 = 1 << 4,
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ICR_RXO = 1 << 6,
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ICR_RXT0 = 1 << 7,
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ICR_MDAC = 1 << 9,
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ICR_TXD_LOW = 1 << 15,
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ICR_SRPD = 1 << 16,
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ICR_ACK = 1 << 17,
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ICR_MNG = 1 << 18,
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ICR_RxQ0 = 1 << 20,
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ICR_RxQ1 = 1 << 21,
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ICR_TxQ0 = 1 << 22,
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ICR_TxQ1 = 1 << 23,
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ICR_Other = 1 << 24,
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};
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enum E1000_IMS : uint32_t
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{
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IMS_TXDW = 1 << 0,
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IMS_TXQE = 1 << 1,
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IMS_LSC = 1 << 2,
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IMS_RXDMT0 = 1 << 4,
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IMS_RXO = 1 << 6,
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IMS_RXT0 = 1 << 7,
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IMS_MDAC = 1 << 9,
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IMS_TXD_LOW = 1 << 15,
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IMS_SRPD = 1 << 16,
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IMS_ACK = 1 << 17,
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IMS_MNG = 1 << 18,
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IMS_RxQ0 = 1 << 20,
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IMS_RxQ1 = 1 << 21,
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IMS_TxQ0 = 1 << 22,
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IMS_TxQ1 = 1 << 23,
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IMS_Other = 1 << 24,
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};
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enum E1000_IMC : uint32_t
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{
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IMC_TXDW = 1 << 0,
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IMC_TXQE = 1 << 1,
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IMC_LSC = 1 << 2,
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IMC_RXDMT0 = 1 << 4,
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IMC_RXO = 1 << 6,
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IMC_RXT0 = 1 << 7,
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IMC_MDAC = 1 << 9,
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IMC_TXD_LOW = 1 << 15,
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IMC_SRPD = 1 << 16,
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IMC_ACK = 1 << 17,
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IMC_MNG = 1 << 18,
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IMC_RxQ0 = 1 << 20,
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IMC_RxQ1 = 1 << 21,
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IMC_TxQ0 = 1 << 22,
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IMC_TxQ1 = 1 << 23,
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IMC_Other = 1 << 24,
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};
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enum E1000_TCTL : uint32_t
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{
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TCTL_EN = 1 << 1,
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TCTL_PSP = 1 << 3,
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TCTL_CT_IEEE = 15 << 4,
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TCTL_SWXOFF = 1 << 22,
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TCTL_PBE = 1 << 23,
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TCTL_RCTL = 1 << 24,
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TCTL_UNORTX = 1 << 25,
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TCTL_MULR = 1 << 28,
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};
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enum E1000_RCTL : uint32_t
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{
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RCTL_EN = 1 << 1,
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RCTL_SBP = 1 << 2,
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RCTL_UPE = 1 << 3,
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RCTL_MPE = 1 << 4,
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RCTL_BAM = 1 << 15,
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RCTL_VFE = 1 << 18,
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RCTL_CFIEN = 1 << 19,
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RCTL_CFI = 1 << 20,
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RCTL_DPF = 1 << 22,
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RCTL_PMCF = 1 << 23,
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RCTL_BSEX = 1 << 25,
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RCTL_SECRC = 1 << 26,
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RCTL_RDMTS_1_2 = 0b00 << 8,
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RCTL_RDMTS_1_4 = 0b01 << 8,
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RCTL_RDMTS_1_8 = 0b10 << 8,
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RCTL_LBM_NORMAL = 0b00 << 6,
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RCTL_LBM_MAC = 0b01 << 6,
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RCTL_BSIZE_256 = (0b11 << 16),
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RCTL_BSIZE_512 = (0b10 << 16),
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RCTL_BSIZE_1024 = (0b01 << 16),
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RCTL_BSIZE_2048 = (0b00 << 16),
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RCTL_BSIZE_4096 = (0b11 << 16) | RCTL_BSEX,
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RCTL_BSIZE_8192 = (0b10 << 16) | RCTL_BSEX,
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RCTL_BSIZE_16384 = (0b01 << 16) | RCTL_BSEX,
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};
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enum E1000_RXCSUM : uint32_t
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{
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RXSUM_IPOFLD = 1 << 8,
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RXSUM_TUOFLD = 1 << 9,
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RXSUM_CRCOFLD = 1 << 11,
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RXSUM_IPPCE = 1 << 12,
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RXSUM_PCSD = 1 << 13,
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};
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enum E1000_CMD : uint8_t
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{
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CMD_EOP = 1 << 0,
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CMD_IFCS = 1 << 1,
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CMD_IC = 1 << 2,
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CMD_RS = 1 << 3,
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CMD_DEXT = 1 << 5,
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CMD_VLE = 1 << 6,
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CMD_IDE = 1 << 7,
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};
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enum E1000_RX_STS : uint8_t
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{
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RX_STS_IPCS = 1 << 6,
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RX_STS_TCPCS = 1 << 5,
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RX_STS_UDPCS = 1 << 5,
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RX_STS_EOP = 1 << 1,
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RX_STS_DD = 1 << 0,
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};
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enum E1000_RX_ERR : uint8_t
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{
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RX_ERR_RXE = 1 << 7,
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RX_ERR_IPE = 1 << 6,
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RX_ERR_TCPE = 1 << 5,
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RX_ERR_CXE = 1 << 4,
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RX_ERR_SEQ = 1 << 2,
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RX_ERR_SE = 1 << 1,
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RX_ERR_CE = 1 << 0,
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};
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struct e1000_rx_desc
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{
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uint64_t addr;
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uint16_t length;
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uint16_t checksum;
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uint8_t status;
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uint8_t errors;
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uint16_t special;
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} __attribute__((packed));
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struct e1000_tx_desc
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{
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uint64_t addr;
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uint16_t length;
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uint8_t cso;
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uint8_t cmd;
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uint8_t status;
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uint8_t css;
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uint16_t special;
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} __attribute__((packed));
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}
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