We now use the correct PIN interrupt from the interrupt line field
instead of writing to it, this had no effect :D
PIN interrupts are now mapped as shared and level triggered, this
properly allows PIN interrupt sharing with multiple devices
There is no need to pass the current mode as an argument as ACPI has
access to that info either way.
Only route INTx objects when using ACPI, they won't be used otherwise
There was a lot of stuff wrong with this driver and it was only getting
speeds of ~2.5 MB/s. Now 4K blocks get ~17 MB/s which is not good but
definitely better. I'm pretty sure the issue is qemu's emulation as 85%
of time is spent between sending the command and it to complete.
Large blocks are now supported too, qemu with block size 1M gets around
600 MB/s read speeds.
The old SpinLockAsMutex was pretty confusing first of all. It also was
causing the issue thats been around for maybe a year now which is the
only consistently happening kernel panic. I've been pretty confused
about this and finally figured out what was causing this.
The main issue was that we were accidentally enabling interrupts when
blocking a thread that passed SpinLockAsMutex from normally interrupt
enabled context. This led to receiving IPI for thread unblock while
we were actively blocking the thread. I'm very suprized this had't
caused any more serious issues than occasional kernel panics :^)
Don't wake up threads when getting the next timer deadline.
If we are idling this can: remove thread from block list, get the
deadline for the next blocked thread, return to idle thread. This will
end up sleeping until the next wake up condition which in the worst
case would be rebalance, or indefinitely when not running SMP.
Make sure we always set the next timer deadline. I was not doing that if
the timer interrupt did not lead to a yield
Scheduler will now set a timer interrupt deadline for when it should get
interrupted next. This fixes a big issue I've had for a long time where
sleeping on an idle core would have to wait for the next periodic
interrupt to wake up. This could cause 1 ms sleeps to be close to 10 ms.
This currently only supports lapic timers and will still fallback to
periodic interrupts when running with PIC. I should add deadline support
to PIT/HPET but why would you run with APIC disabled ;)
`sleep` is now implemented in terms of `nanosleep`. `nanosleep` is now
more precise and handles overflow when calculating wakeup time. I don't
think anything was depending on this, but I could see a program sleeping
for max time to block until signal.
There is no need to read and write the receive tail pointer for every
packet. This change bumped my TCP speed from ~11MB/s to ~40MB/s which is
my network speed limit
This now works properly on real hardware. Main issue was a race
condition with now ISR was handled in the interrupt handler. We now loop
until we read back ISR as zero
Bananymous