Kernel: Paging uses now PAE with 2 MiB pages
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Bananymous
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a12ddfa12a
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d6623def32
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@ -211,7 +211,7 @@ namespace APIC
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static void ParseMADT(RSDPDescriptor* rsdp)
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{
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RSDT* root = (RSDT*)(rsdp->revision == 2 ? ((RSDPDescriptor20*)rsdp)->xsdt_address : rsdp->rsdt_address);
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Paging::MapRSDP((uint32_t)root & 0xFFC00000);
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Paging::MapPage((uint32_t)root);
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uint32_t sdt_entry_count = (root->header.length - sizeof(root->header)) / (rsdp->revision == 2 ? 8 : 4);
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for (uint32_t i = 0; i < sdt_entry_count; i++)
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@ -372,10 +372,8 @@ namespace APIC
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if (s_local_apic == 0 || s_io_apic == 0)
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return false;
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if ((s_io_apic & 0xFFC00000) != (s_local_apic & 0xFFC00000))
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Kernel::panic("lapic and ioapic are not in the same 4 MiB are");
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Paging::MapAPIC(s_io_apic & 0xFFC00000);
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Paging::MapPage(s_io_apic);
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Paging::MapPage(s_local_apic);
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// Enable Local APIC
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SetMSR(IA32_APIC_BASE, (s_local_apic & 0xFFFFF000) | IA32_APIC_BASE_ENABLE, 0);
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@ -1,66 +1,88 @@
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#include <kernel/CPUID.h>
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#include <kernel/Paging.h>
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#include <kernel/panic.h>
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#include <string.h>
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#define PRESENT (1 << 0)
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#define READ_WRITE (1 << 1)
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#define PAGE_SIZE (1 << 7)
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namespace Paging
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{
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static uint32_t s_page_directory[1024] __attribute__((aligned(4096)));
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static uint32_t s_page_table[1024] __attribute__((aligned(4096)));
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static uint32_t s_page_table_framebuffer[1024] __attribute__((aligned(4096)));
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static uint32_t s_page_table_rsdp[1024] __attribute__((aligned(4096)));
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static uint32_t s_page_table_apic[1024] __attribute__((aligned(4096)));
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static uint64_t s_page_directory_pointer_table[4] __attribute__((aligned(0x20)));
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static uint64_t s_page_directory[4 * 512] __attribute__((aligned(4096)));
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static bool HasRequirements()
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{
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uint32_t ecx, edx;
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CPUID::GetFeatures(ecx, edx);
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if (!(edx & CPUID::Features::EDX_PAE))
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{
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derrorln("PAE not supported, halting");
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return false;
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}
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return true;
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}
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void Initialize()
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{
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for (uint32_t i = 0; i < 1024; i++)
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s_page_directory[i] = 0x00000002;
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if (!HasRequirements())
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asm volatile("hlt");
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for (uint32_t i = 0; i < 1024; i++)
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s_page_table[i] = (i << 12) | 0x03;
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s_page_directory[0] = (uint32_t)s_page_table | 0x03;
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// Identity map first 2 (2 MiB) pages
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memset(s_page_directory, 0x00, sizeof(s_page_directory));
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s_page_directory[0] = (0x00 << 21) | PAGE_SIZE | READ_WRITE | PRESENT;
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s_page_directory[1] = (0x01 << 21) | PAGE_SIZE | READ_WRITE | PRESENT;
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// Initialize PDPTEs
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for (int i = 0; i < 4; i++)
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s_page_directory_pointer_table[i] = (uint64_t)(&s_page_directory[512 * i]) | PRESENT;
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asm volatile(
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"movl %%eax, %%cr3;"
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// Enable PAE
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"movl %%cr4, %%eax;"
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"orl $0x20, %%eax;"
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"movl %%eax, %%cr4;"
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// Load PDPT address to cr3
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"movl %0, %%cr3;"
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// Enable paging
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"movl %%cr0, %%eax;"
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"orl $0x80000001, %%eax;"
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"orl $0x80000000, %%eax;"
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"movl %%eax, %%cr0;"
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:: "a"(s_page_directory)
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:: "r" (s_page_directory_pointer_table)
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: "eax"
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);
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dprintln("Paging enabled");
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}
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static void MapPDE(uint32_t address, uint32_t* pt)
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void MapPage(uintptr_t address)
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{
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if ((address & 0xffc00000) != address)
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Kernel::panic("Trying to map non 4 MiB aligned address");
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uint32_t pd_index = address >> 22;
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if (!(s_page_directory[pd_index] & (1 << 0)))
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if (address != ((address >> 21) << 21))
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{
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// Identity map the whole page table
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for (uint32_t i = 0; i < 1024; i++)
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pt[i] = address | (i << 12) | 0x03;
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// Set the pde to point to page table
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s_page_directory[pd_index] = (uint32_t)pt | 0x03;
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// Flush TLB
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for (uint32_t i = 0; i < 1024; i++)
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asm volatile("invlpg (%0)" :: "r" (address | (i << 12)) : "memory");
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dprintln("aligning 0x{8H} to 2 MiB boundary -> 0x{8H}", address, (address >> 21) << 21);
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address = (address >> 21) << 21;
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}
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}
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void MapFramebuffer(uint32_t address)
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{
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MapPDE(address, s_page_table_framebuffer);
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}
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uint32_t pde = address >> 21;
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void MapRSDP(uint32_t address)
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{
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MapPDE(address, s_page_table_rsdp);
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}
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dprintln("mapping pde {} (0x{8H} - 0x{8H})", pde, pde << 21, ((pde + 1) << 21) - 1);
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void MapAPIC(uint32_t address)
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{
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MapPDE(address, s_page_table_apic);
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if (s_page_directory[pde] & PRESENT)
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{
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dprintln("page already mapped");
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return;
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}
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// Map and flush the given address
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s_page_directory[pde] = address | PAGE_SIZE | READ_WRITE | PRESENT;
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asm volatile("invlpg (%0)" :: "r"(address) : "memory");
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}
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}
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@ -95,7 +95,7 @@ namespace VESA
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s_height = framebuffer.height;
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s_mode = framebuffer.type;
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Paging::MapFramebuffer(framebuffer.addr & 0xFFC00000);
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Paging::MapPage(framebuffer.addr);
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if (s_mode == MULTIBOOT_FRAMEBUFFER_TYPE_GRAPHICS)
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{
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@ -7,8 +7,6 @@ namespace Paging
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void Initialize();
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void MapFramebuffer(uint32_t address);
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void MapRSDP(uint32_t address);
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void MapAPIC(uint32_t address);
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void MapPage(uintptr_t address);
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}
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