88 lines
2.0 KiB
C++
88 lines
2.0 KiB
C++
#include <kernel/CPUID.h>
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#include <kernel/Paging.h>
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#include <kernel/panic.h>
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#include <string.h>
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#define PRESENT (1 << 0)
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#define READ_WRITE (1 << 1)
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#define PAGE_SIZE (1 << 7)
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namespace Paging
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{
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static uint64_t s_page_directory_pointer_table[4] __attribute__((aligned(0x20)));
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static uint64_t s_page_directory[4 * 512] __attribute__((aligned(4096)));
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static bool HasRequirements()
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{
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uint32_t ecx, edx;
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CPUID::GetFeatures(ecx, edx);
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if (!(edx & CPUID::Features::EDX_PAE))
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{
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derrorln("PAE not supported, halting");
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return false;
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}
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return true;
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}
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void Initialize()
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{
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if (!HasRequirements())
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asm volatile("hlt");
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// Identity map first 2 (2 MiB) pages
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memset(s_page_directory, 0x00, sizeof(s_page_directory));
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s_page_directory[0] = (0x00 << 21) | PAGE_SIZE | READ_WRITE | PRESENT;
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s_page_directory[1] = (0x01 << 21) | PAGE_SIZE | READ_WRITE | PRESENT;
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// Initialize PDPTEs
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for (int i = 0; i < 4; i++)
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s_page_directory_pointer_table[i] = (uint64_t)(&s_page_directory[512 * i]) | PRESENT;
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asm volatile(
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// Enable PAE
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"movl %%cr4, %%eax;"
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"orl $0x20, %%eax;"
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"movl %%eax, %%cr4;"
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// Load PDPT address to cr3
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"movl %0, %%cr3;"
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// Enable paging
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"movl %%cr0, %%eax;"
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"orl $0x80000000, %%eax;"
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"movl %%eax, %%cr0;"
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:: "r" (s_page_directory_pointer_table)
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: "eax"
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);
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dprintln("Paging enabled");
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}
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void MapPage(uintptr_t address)
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{
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if (address != ((address >> 21) << 21))
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{
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dprintln("aligning 0x{8H} to 2 MiB boundary -> 0x{8H}", address, (address >> 21) << 21);
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address = (address >> 21) << 21;
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}
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uint32_t pde = address >> 21;
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dprintln("mapping pde {} (0x{8H} - 0x{8H})", pde, pde << 21, ((pde + 1) << 21) - 1);
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if (s_page_directory[pde] & PRESENT)
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{
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dprintln("page already mapped");
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return;
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}
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// Map and flush the given address
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s_page_directory[pde] = address | PAGE_SIZE | READ_WRITE | PRESENT;
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asm volatile("invlpg (%0)" :: "r"(address) : "memory");
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}
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} |