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banan-os/kernel/arch/i686/interrupts.S

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Kernel: Save segment registers on all interrupts on i686
2024-04-03 00:41:13 +03:00
.macro push_userspace
pushw %gs
pushw %fs
pushw %es
pushw %ds
pushal
.endm
.macro load_kernel_segments
movw $0x10, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %fs
movw $0x28, %ax
movw %ax, %gs
.endm
.macro pop_userspace
popal
popw %ds
popw %es
popw %fs
popw %gs
.endm
Kernel: Unify IDT and GDT code between x86_64 and x86_32 The code is pretty much the same, so there are just couple macros differiating initialization.
2024-03-26 13:59:09 +02:00
isr_stub:
Kernel: Save segment registers on all interrupts on i686
2024-04-03 00:41:13 +03:00
push_userspace
load_kernel_segments
Kernel: Write isr handler for x86_32 and cleanup x86_64
2024-03-26 16:36:51 +02:00
movl %cr0, %eax; pushl %eax
movl %cr2, %eax; pushl %eax
movl %cr3, %eax; pushl %eax
movl %cr4, %eax; pushl %eax
movl %esp, %eax // register ptr
Kernel: Save segment registers on all interrupts on i686
2024-04-03 00:41:13 +03:00
leal 64(%esp), %ebx // interrupt stack ptr
movl 60(%esp), %ecx // error code
movl 56(%esp), %edx // isr number
Kernel: Write isr handler for x86_32 and cleanup x86_64
2024-03-26 16:36:51 +02:00
Kernel: Make sure stack is aligned on interrupts for i686 target I just realized that only x86_64 aligns stack pointer when interrupt is triggered.
2024-07-22 00:10:42 +03:00
movl %esp, %ebp
subl $15, %esp
andl $0xFFFFFFF0, %esp
Kernel: Write isr handler for x86_32 and cleanup x86_64
2024-03-26 16:36:51 +02:00
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
Kernel: Unify IDT and GDT code between x86_64 and x86_32 The code is pretty much the same, so there are just couple macros differiating initialization.
2024-03-26 13:59:09 +02:00
call cpp_isr_handler
Kernel: Make sure stack is aligned on interrupts for i686 target I just realized that only x86_64 aligns stack pointer when interrupt is triggered.
2024-07-22 00:10:42 +03:00
movl %ebp, %esp
addl $16, %esp
Kernel: Write isr handler for x86_32 and cleanup x86_64
2024-03-26 16:36:51 +02:00
Kernel: Save segment registers on all interrupts on i686
2024-04-03 00:41:13 +03:00
pop_userspace
Kernel: Write isr handler for x86_32 and cleanup x86_64
2024-03-26 16:36:51 +02:00
addl $8, %esp
Kernel: Unify IDT and GDT code between x86_64 and x86_32 The code is pretty much the same, so there are just couple macros differiating initialization.
2024-03-26 13:59:09 +02:00
iret
irq_stub:
Kernel: Save segment registers on all interrupts on i686
2024-04-03 00:41:13 +03:00
push_userspace
load_kernel_segments
Kernel: Write isr handler for x86_32 and cleanup x86_64
2024-03-26 16:36:51 +02:00
Kernel: Save segment registers on all interrupts on i686
2024-04-03 00:41:13 +03:00
movl 40(%esp), %eax # interrupt number
Kernel: Rework scheduler/processor stacks.
2024-04-02 12:34:42 +03:00
Kernel: Make sure stack is aligned on interrupts for i686 target I just realized that only x86_64 aligns stack pointer when interrupt is triggered.
2024-07-22 00:10:42 +03:00
movl %esp, %ebp
subl $15, %esp
andl $0xFFFFFFF0, %esp
Kernel: Save segment registers on all interrupts on i686
2024-04-03 00:41:13 +03:00
subl $12, %esp
Kernel: Rework scheduler/processor stacks.
2024-04-02 12:34:42 +03:00
pushl %eax
call cpp_irq_handler
Kernel: Make sure stack is aligned on interrupts for i686 target I just realized that only x86_64 aligns stack pointer when interrupt is triggered.
2024-07-22 00:10:42 +03:00
movl %ebp, %esp
Kernel: Rework scheduler/processor stacks.
2024-04-02 12:34:42 +03:00
Kernel: Save segment registers on all interrupts on i686
2024-04-03 00:41:13 +03:00
pop_userspace
Kernel: Rework scheduler/processor stacks.
2024-04-02 12:34:42 +03:00
addl $8, %esp
iret
Kernel: Fix multiprocessor for i686 i686 is now actually ran with multiple processors.
2024-04-03 14:42:17 +03:00
.global asm_yield_handler
asm_yield_handler:
# This can only be called from kernel, so no segment saving is needed
pushal
Kernel: Rework scheduler/processor stacks.
2024-04-02 12:34:42 +03:00
movl %esp, %eax # interrupt registers ptr
Kernel: Fix multiprocessor for i686 i686 is now actually ran with multiple processors.
2024-04-03 14:42:17 +03:00
leal 32(%esp), %ebx # interrupt stack ptr
Kernel: Write isr handler for x86_32 and cleanup x86_64
2024-03-26 16:36:51 +02:00
Kernel: Make sure stack is aligned on interrupts for i686 target I just realized that only x86_64 aligns stack pointer when interrupt is triggered.
2024-07-22 00:10:42 +03:00
movl %esp, %ebp
subl $15, %esp
andl $0xFFFFFFF0, %esp
subl $8, %esp
Kernel: Write isr handler for x86_32 and cleanup x86_64
2024-03-26 16:36:51 +02:00
pushl %eax
pushl %ebx
Kernel: Fix multiprocessor for i686 i686 is now actually ran with multiple processors.
2024-04-03 14:42:17 +03:00
call cpp_yield_handler
Kernel: Make sure stack is aligned on interrupts for i686 target I just realized that only x86_64 aligns stack pointer when interrupt is triggered.
2024-07-22 00:10:42 +03:00
movl %ebp, %esp
Kernel: Unify IDT and GDT code between x86_64 and x86_32 The code is pretty much the same, so there are just couple macros differiating initialization.
2024-03-26 13:59:09 +02:00
Kernel: Fix multiprocessor for i686 i686 is now actually ran with multiple processors.
2024-04-03 14:42:17 +03:00
popal
Kernel: Unify IDT and GDT code between x86_64 and x86_32 The code is pretty much the same, so there are just couple macros differiating initialization.
2024-03-26 13:59:09 +02:00
iret
Kernel: Rewrite the whole scheduler and re-architecture SMP handling Change Semaphore -> ThreadBlocker This was not a semaphore, I just named it one because I didn't know what semaphore was. I have meant to change this sooner, but it was in no way urgent :D Implement SMP events. Processors can now be sent SMP events through IPIs. SMP events can be sent either to a single processor or broadcasted to every processor. PageTable::{map_page,map_range,unmap_page,unmap_range}() now send SMP event to invalidate TLB caches for the changed pages. Scheduler no longer uses a global run queue. Each processor has its own scheduler that keeps track of the load on the processor. Once every second schedulers do load balancing. Schedulers have no access to other processors' schedulers, they just see approximate loads. If scheduler decides that it has too much load, it will send a thread to another processor through a SMP event. Schedulers are currently run using the timer interrupt on BSB. This should be not the case, and each processor should use its LAPIC timer for interrupts. There is no reason to broadcast SMP event to all processors when BSB gets timer interrupt. Old scheduler only achieved 20% idle load on qemu. That was probably a very inefficient implementation. This new scheduler seems to average around 1% idle load. This is much closer to what I would expect. On my own laptop idle load seems to be only around 0.5% on each processor.
2024-07-22 00:33:50 +03:00
.global asm_ipi_handler
asm_ipi_handler:
push_userspace
load_kernel_segments
movl %esp, %ebp
subl $15, %esp
andl $0xFFFFFFF0, %esp
call cpp_ipi_handler
movl %ebp, %esp
pop_userspace
iret
Kernel: All processors use LAPIC timer when running with APIC This makes scheduler preemption much cleaner as bsb does not have to send smp messages to notify other processes about timer interrupt. Also PIT percision is now "full" 0.8 us instead of 1 ms that I was using before.
2024-07-23 02:28:52 +03:00
.global asm_timer_handler
asm_timer_handler:
push_userspace
load_kernel_segments
movl %esp, %ebp
subl $15, %esp
andl $0xFFFFFFF0, %esp
call cpp_timer_handler
movl %ebp, %esp
pop_userspace
iret
Kernel: Unify IDT and GDT code between x86_64 and x86_32 The code is pretty much the same, so there are just couple macros differiating initialization.
2024-03-26 13:59:09 +02:00
.macro isr n
.global isr\n
isr\n:
pushl $0
pushl $\n
jmp isr_stub
.endm
.macro isr_err n
.global isr\n
isr\n:
pushl $\n
jmp isr_stub
.endm
.macro irq n
.global irq\n
irq\n:
pushl $0
pushl $\n
jmp irq_stub
.endm
isr 0
isr 1
isr 2
isr 3
isr 4
isr 5
isr 6
isr 7
isr_err 8
isr 9
isr_err 10
isr_err 11
isr_err 12
isr_err 13
isr_err 14
isr 15
isr 16
isr_err 17
isr 18
isr 19
isr 20
isr 21
isr 22
isr 23
isr 24
isr 25
isr 26
isr 27
isr 28
isr 29
isr 30
isr 31
irq 0
irq 1
irq 2
irq 3
irq 4
irq 5
irq 6
irq 7
irq 8
irq 9
irq 10
irq 11
irq 12
irq 13
irq 14
irq 15
irq 16
irq 17
irq 18
irq 19
irq 20
irq 21
irq 22
irq 23
irq 24
irq 25
irq 26
irq 27
irq 28
irq 29
irq 30
irq 31
Kernel: Fix interrupt system I had not understood how MSIs work and I was unnecessarily routing them through IOAPIC. This is not necessary and should not be done :D Also MSIs were reserving interrupts that IOAPIC was capable of generating. Now IOAPIC and MSIs use different set of interrupts so IOAPIC can use more interrupts if needed.
2024-09-27 15:31:31 +03:00
irq 32
irq 33
irq 34
irq 35
irq 36
irq 37
irq 38
irq 39
irq 40
irq 41
irq 42
irq 43
irq 44
irq 45
irq 46
irq 47
irq 48
irq 49
irq 50
irq 51
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irq 207