Bananymous
4af9699b22
There is no need to save and load sse state on every interrupt. Instead we can use CR0.TS to make threads trigger an interrupt when they use sse instructions. This can be used to only save and load sse state when needed. Processor now keeps track of its current "sse thread" and the scheduler either enabled or disabled sse based on which thread it is starting up. When a thread dies, it checks if it was the current sse thread to avoid use after free bugs. When load balancing, processor has to save the thread's sse state before sending it to a new processor (if it was the current sse thread). This ensures thread's sse state will be correct when the new processor ends up loading it.
49 lines
696 B
ArmAsm
49 lines
696 B
ArmAsm
# uint32_t read_ip()
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.global read_ip
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read_ip:
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popl %eax
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jmp *%eax
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# void start_kernel_thread()
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.global start_kernel_thread
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start_kernel_thread:
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call get_thread_start_sp
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movl %eax, %esp
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# STACK LAYOUT
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# on_exit arg
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# on_exit func
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# entry arg
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# entry func
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movl 4(%esp), %edi
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movl 0(%esp), %esi
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subl $12, %esp
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pushl %edi
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sti
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call *%esi
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addl $16, %esp
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movl 12(%esp), %edi
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movl 8(%esp), %esi
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subl $12, %esp
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pushl %edi
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call *%esi
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.global start_userspace_thread
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start_userspace_thread:
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call get_thread_start_sp
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movl %eax, %esp
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movw $(0x20 | 3), %bx
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movw %bx, %ds
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movw %bx, %es
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movw $(0x30 | 3), %bx
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movw %bx, %fs
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movw $(0x38 | 3), %bx
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movw %bx, %gs
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iret
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