317 lines
7.5 KiB
C++
317 lines
7.5 KiB
C++
#include <kernel/IDT.h>
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#include <kernel/InterruptController.h>
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#include <kernel/IO.h>
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#include <kernel/Memory/PageTable.h>
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#include <kernel/MMIO.h>
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#include <kernel/Networking/E1000/E1000.h>
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#include <kernel/Networking/NetworkManager.h>
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#define DEBUG_E1000 1
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namespace Kernel
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{
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// https://www.intel.com/content/dam/doc/manual/pci-pci-x-family-gbe-controllers-software-dev-manual.pdf (section 5.2)
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bool E1000::probe(PCI::Device& pci_device)
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{
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// Intel device
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if (pci_device.vendor_id() != 0x8086)
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return false;
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switch (pci_device.device_id())
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{
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case 0x1019:
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case 0x101A:
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case 0x1010:
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case 0x1012:
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case 0x101D:
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case 0x1079:
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case 0x107A:
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case 0x107B:
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case 0x100F:
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case 0x1011:
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case 0x1026:
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case 0x1027:
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case 0x1028:
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case 0x1107:
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case 0x1112:
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case 0x1013:
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case 0x1018:
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case 0x1076:
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case 0x1077:
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case 0x1078:
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case 0x1017:
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case 0x1016:
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case 0x100e:
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case 0x1015:
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return true;
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default:
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return false;
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}
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}
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BAN::ErrorOr<BAN::RefPtr<E1000>> E1000::create(PCI::Device& pci_device)
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{
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auto e1000 = TRY(BAN::RefPtr<E1000>::create(pci_device));
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TRY(e1000->initialize());
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return e1000;
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}
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E1000::~E1000()
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{
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}
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BAN::ErrorOr<void> E1000::initialize()
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{
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m_bar_region = TRY(m_pci_device.allocate_bar_region(0));
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m_pci_device.enable_bus_mastering();
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detect_eeprom();
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TRY(read_mac_address());
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#if DEBUG_E1000
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dprintln("E1000 at PCI {}:{}.{}", m_pci_device.bus(), m_pci_device.dev(), m_pci_device.func());
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dprintln(" MAC: {}", m_mac_address);
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#endif
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TRY(initialize_rx());
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TRY(initialize_tx());
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enable_link();
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TRY(enable_interrupt());
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m_link_up = !!(read32(REG_STATUS) & STATUS_LU);
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#if DEBUG_E1000
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dprintln(" link up: {}", link_up());
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if (link_up())
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{
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int speed = link_speed();
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dprintln(" link speed: {} Mbps", speed);
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}
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#endif
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return {};
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}
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void E1000::write32(uint16_t reg, uint32_t value)
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{
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m_bar_region->write32(reg, value);
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}
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uint32_t E1000::read32(uint16_t reg)
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{
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return m_bar_region->read32(reg);
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}
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void E1000::detect_eeprom()
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{
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m_has_eerprom = false;
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write32(REG_EERD, 0x01);
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for (int i = 0; i < 1000 && !m_has_eerprom; i++)
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if (read32(REG_EERD) & 0x10)
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m_has_eerprom = true;
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}
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uint32_t E1000::eeprom_read(uint8_t address)
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{
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uint32_t tmp = 0;
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if (m_has_eerprom)
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{
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write32(REG_EERD, ((uint32_t)address << 8) | 1);
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while (!((tmp = read32(REG_EERD)) & (1 << 4)))
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continue;
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}
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else
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{
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write32(REG_EERD, ((uint32_t)address << 2) | 1);
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while (!((tmp = read32(REG_EERD)) & (1 << 1)))
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continue;
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}
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return (tmp >> 16) & 0xFFFF;
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}
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BAN::ErrorOr<void> E1000::read_mac_address()
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{
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if (m_has_eerprom)
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{
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uint32_t temp = eeprom_read(0);
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m_mac_address.address[0] = temp;
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m_mac_address.address[1] = temp >> 8;
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temp = eeprom_read(1);
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m_mac_address.address[2] = temp;
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m_mac_address.address[3] = temp >> 8;
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temp = eeprom_read(2);
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m_mac_address.address[4] = temp;
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m_mac_address.address[5] = temp >> 8;
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return {};
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}
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if (read32(0x5400) == 0)
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{
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dwarnln("no mac address");
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return BAN::Error::from_errno(EINVAL);
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}
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for (int i = 0; i < 6; i++)
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m_mac_address.address[i] = (uint8_t)read32(0x5400 + i * 8);
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return {};
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}
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BAN::ErrorOr<void> E1000::initialize_rx()
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{
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m_rx_buffer_region = TRY(DMARegion::create(E1000_RX_BUFFER_SIZE * E1000_RX_DESCRIPTOR_COUNT));
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m_rx_descriptor_region = TRY(DMARegion::create(sizeof(e1000_rx_desc) * E1000_RX_DESCRIPTOR_COUNT));
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auto* rx_descriptors = reinterpret_cast<volatile e1000_rx_desc*>(m_rx_descriptor_region->vaddr());
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for (size_t i = 0; i < E1000_RX_DESCRIPTOR_COUNT; i++)
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{
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rx_descriptors[i].addr = m_rx_buffer_region->paddr() + E1000_RX_BUFFER_SIZE * i;
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rx_descriptors[i].status = 0;
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}
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uint64_t paddr64 = m_rx_descriptor_region->paddr();
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write32(REG_RDBAL0, paddr64 & 0xFFFFFFFF);
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write32(REG_RDBAH0, paddr64 >> 32);
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write32(REG_RDLEN0, E1000_RX_DESCRIPTOR_COUNT * sizeof(e1000_rx_desc));
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write32(REG_RDH0, 0);
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write32(REG_RDT0, E1000_RX_DESCRIPTOR_COUNT - 1);
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uint32_t rctrl = 0;
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rctrl |= RCTL_EN;
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rctrl |= RCTL_SBP;
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rctrl |= RCTL_UPE;
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rctrl |= RCTL_MPE;
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rctrl |= RCTL_LBM_NORMAL;
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rctrl |= RCTL_RDMTS_1_2;
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rctrl |= RCTL_BAM;
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rctrl |= RCTL_SECRC;
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rctrl |= RCTL_BSIZE_8192;
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write32(REG_RCTL, rctrl);
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return {};
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}
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BAN::ErrorOr<void> E1000::initialize_tx()
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{
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m_tx_buffer_region = TRY(DMARegion::create(E1000_TX_BUFFER_SIZE * E1000_TX_DESCRIPTOR_COUNT));
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m_tx_descriptor_region = TRY(DMARegion::create(sizeof(e1000_tx_desc) * E1000_TX_DESCRIPTOR_COUNT));
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auto* tx_descriptors = reinterpret_cast<volatile e1000_tx_desc*>(m_tx_descriptor_region->vaddr());
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for (size_t i = 0; i < E1000_TX_DESCRIPTOR_COUNT; i++)
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{
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tx_descriptors[i].addr = m_tx_buffer_region->paddr() + E1000_TX_BUFFER_SIZE * i;
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tx_descriptors[i].cmd = 0;
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}
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uint64_t paddr64 = m_tx_descriptor_region->paddr();
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write32(REG_TDBAL, paddr64 & 0xFFFFFFFF);
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write32(REG_TDBAH, paddr64 >> 32);
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write32(REG_TDLEN, E1000_TX_DESCRIPTOR_COUNT * sizeof(e1000_tx_desc));
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write32(REG_TDH, 0);
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write32(REG_TDT, 0);
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write32(REG_TCTL, TCTL_EN | TCTL_PSP);
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write32(REG_TIPG, 0x0060200A);
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return {};
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}
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void E1000::enable_link()
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{
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write32(REG_CTRL, read32(REG_CTRL) | CTRL_SLU);
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}
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int E1000::link_speed()
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{
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if (!link_up())
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return 0;
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uint32_t speed = read32(REG_STATUS) & STATUS_SPEED_MASK;
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if (speed == STATUS_SPEED_10MB)
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return 10;
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if (speed == STATUS_SPEED_100MB)
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return 100;
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if (speed == STATUS_SPEED_1000MB1)
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return 1000;
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if (speed == STATUS_SPEED_1000MB2)
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return 1000;
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return 0;
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}
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BAN::ErrorOr<void> E1000::enable_interrupt()
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{
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write32(REG_ITR, 0x1000);
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write32(REG_IVAR, 1 << 3);
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write32(REG_EITR, 0x1000);
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write32(REG_IMS, IMC_RxQ0);
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read32(REG_ICR);
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TRY(m_pci_device.reserve_irqs(1));
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set_irq(m_pci_device.get_irq(0));
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Interruptable::enable_interrupt();
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return {};
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}
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BAN::ErrorOr<void> E1000::send_bytes(BAN::MACAddress destination, EtherType protocol, BAN::ConstByteSpan buffer)
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{
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ASSERT(buffer.size() + sizeof(EthernetHeader) <= E1000_TX_BUFFER_SIZE);
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SpinLockGuard _(m_lock);
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size_t tx_current = read32(REG_TDT) % E1000_TX_DESCRIPTOR_COUNT;
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auto* tx_buffer = reinterpret_cast<uint8_t*>(m_tx_buffer_region->vaddr() + E1000_TX_BUFFER_SIZE * tx_current);
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auto& ethernet_header = *reinterpret_cast<EthernetHeader*>(tx_buffer);
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ethernet_header.dst_mac = destination;
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ethernet_header.src_mac = get_mac_address();
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ethernet_header.ether_type = protocol;
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memcpy(tx_buffer + sizeof(EthernetHeader), buffer.data(), buffer.size());
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auto& descriptor = reinterpret_cast<volatile e1000_tx_desc*>(m_tx_descriptor_region->vaddr())[tx_current];
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descriptor.length = sizeof(EthernetHeader) + buffer.size();
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descriptor.status = 0;
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descriptor.cmd = CMD_EOP | CMD_IFCS | CMD_RS;
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write32(REG_TDT, (tx_current + 1) % E1000_TX_DESCRIPTOR_COUNT);
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while (descriptor.status == 0)
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continue;
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return {};
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}
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void E1000::handle_irq()
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{
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if (read32(REG_ICR) & ICR_RxQ0)
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return;
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SpinLockGuard _(m_lock);
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for (;;) {
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uint32_t rx_current = (read32(REG_RDT0) + 1) % E1000_RX_DESCRIPTOR_COUNT;
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auto& descriptor = reinterpret_cast<volatile e1000_rx_desc*>(m_rx_descriptor_region->vaddr())[rx_current];
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if (!(descriptor.status & 1))
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break;
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ASSERT(descriptor.length <= E1000_RX_BUFFER_SIZE);
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NetworkManager::get().on_receive(*this, BAN::ConstByteSpan {
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reinterpret_cast<const uint8_t*>(m_rx_buffer_region->vaddr() + rx_current * E1000_RX_BUFFER_SIZE),
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descriptor.length
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});
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descriptor.status = 0;
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write32(REG_RDT0, rx_current);
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}
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}
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}
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