623 lines
16 KiB
C++
623 lines
16 KiB
C++
#include <kernel/IDT.h>
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#include <kernel/IO.h>
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#include <kernel/Memory/PageTable.h>
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#include <kernel/MMIO.h>
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#include <kernel/Networking/NetworkManager.h>
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#include <kernel/PCI.h>
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#include <kernel/Storage/ATA/AHCI/Controller.h>
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#include <kernel/Storage/ATA/ATAController.h>
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#include <kernel/Storage/NVMe/Controller.h>
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#define INVALID_VENDOR 0xFFFF
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#define MULTI_FUNCTION 0x80
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#define CONFIG_ADDRESS 0xCF8
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#define CONFIG_DATA 0xCFC
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#define PCI_REG_COMMAND 0x04
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#define PCI_REG_STATUS 0x06
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#define PCI_REG_CAPABILITIES 0x34
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#define PCI_REG_IRQ_LINE 0x3C
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#define PCI_REG_IRQ_PIN 0x44
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#define PCI_CMD_IO_SPACE (1 << 0)
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#define PCI_CMD_MEM_SPACE (1 << 1)
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#define PCI_CMD_BUS_MASTER (1 << 2)
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#define PCI_CMD_INTERRUPT_DISABLE (1 << 10)
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#define DEBUG_PCI 0
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namespace Kernel::PCI
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{
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static PCIManager* s_instance = nullptr;
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struct MSIXEntry
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{
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uint32_t msg_addr_low;
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uint32_t msg_addr_high;
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uint32_t msg_data;
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uint32_t vector_ctrl;
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};
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static_assert(sizeof(MSIXEntry) == 16);
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uint32_t PCIManager::read_config_dword(uint8_t bus, uint8_t dev, uint8_t func, uint8_t offset)
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{
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ASSERT(offset % 4 == 0);
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uint32_t config_addr = 0x80000000 | ((uint32_t)bus << 16) | ((uint32_t)dev << 11) | ((uint32_t)func << 8) | offset;
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IO::outl(CONFIG_ADDRESS, config_addr);
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return IO::inl(CONFIG_DATA);
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}
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uint16_t PCIManager::read_config_word(uint8_t bus, uint8_t dev, uint8_t func, uint8_t offset)
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{
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ASSERT(offset % 2 == 0);
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uint32_t dword = read_config_dword(bus, dev, func, offset & ~3);
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return (dword >> ((offset & 3) * 8)) & 0xFFFF;
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}
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uint8_t PCIManager::read_config_byte(uint8_t bus, uint8_t dev, uint8_t func, uint8_t offset)
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{
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uint32_t dword = read_config_dword(bus, dev, func, offset & ~3);
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return (dword >> ((offset & 3) * 8)) & 0xFF;
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}
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void PCIManager::write_config_dword(uint8_t bus, uint8_t dev, uint8_t func, uint8_t offset, uint32_t value)
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{
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ASSERT(offset % 4 == 0);
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uint32_t config_addr = 0x80000000 | ((uint32_t)bus << 16) | ((uint32_t)dev << 11) | ((uint32_t)func << 8) | offset;
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IO::outl(CONFIG_ADDRESS, config_addr);
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IO::outl(CONFIG_DATA, value);
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}
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void PCIManager::write_config_word(uint8_t bus, uint8_t dev, uint8_t func, uint8_t offset, uint16_t value)
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{
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ASSERT(offset % 2 == 0);
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uint32_t byte = (offset & 3) * 8;
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uint32_t temp = read_config_dword(bus, dev, func, offset & ~3);
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temp &= ~(0xFFFF << byte);
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temp |= (uint32_t)value << byte;
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write_config_dword(bus, dev, func, offset & ~3, temp);
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}
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void PCIManager::write_config_byte(uint8_t bus, uint8_t dev, uint8_t func, uint8_t offset, uint8_t value)
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{
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uint32_t byte = (offset & 3) * 8;
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uint32_t temp = read_config_dword(bus, dev, func, offset & ~3);
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temp &= ~(0xFF << byte);
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temp |= (uint32_t)value << byte;
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write_config_dword(bus, dev, func, offset & ~3, temp);
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}
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static uint16_t get_vendor_id(uint8_t bus, uint8_t dev, uint8_t func)
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{
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uint32_t dword = PCIManager::read_config_dword(bus, dev, func, 0x00);
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return dword & 0xFFFF;
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}
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static uint8_t get_header_type(uint8_t bus, uint8_t dev, uint8_t func)
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{
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uint32_t dword = PCIManager::read_config_dword(bus, dev, func, 0x0C);
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return (dword >> 16) & 0xFF;
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}
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void PCIManager::initialize()
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{
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ASSERT(s_instance == nullptr);
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s_instance = new PCIManager();
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ASSERT(s_instance);
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s_instance->check_all_buses();
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s_instance->initialize_devices();
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}
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PCIManager& PCIManager::get()
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{
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ASSERT(s_instance);
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return *s_instance;
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}
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void PCIManager::check_function(uint8_t bus, uint8_t dev, uint8_t func)
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{
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MUST(m_devices.emplace_back(bus, dev, func));
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auto& device = m_devices.back();
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if (device.class_code() == 0x06 && device.subclass() == 0x04)
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check_bus(device.read_byte(0x19));
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}
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void PCIManager::check_device(uint8_t bus, uint8_t dev)
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{
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if (get_vendor_id(bus, dev, 0) == INVALID_VENDOR)
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return;
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check_function(bus, dev, 0);
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if (get_header_type(bus, dev, 0) & MULTI_FUNCTION)
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for (uint8_t func = 1; func < 8; func++)
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if (get_vendor_id(bus, dev, func) != INVALID_VENDOR)
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check_function(bus, dev, func);
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}
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void PCIManager::check_bus(uint8_t bus)
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{
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for (uint8_t dev = 0; dev < 32; dev++)
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check_device(bus, dev);
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}
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void PCIManager::check_all_buses()
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{
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if (get_header_type(0, 0, 0) & MULTI_FUNCTION)
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{
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for (int func = 0; func < 8 && get_vendor_id(0, 0, func) != INVALID_VENDOR; func++)
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check_bus(func);
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}
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else
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{
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check_bus(0);
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}
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}
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void PCIManager::initialize_devices()
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{
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for (auto& pci_device : m_devices)
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{
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switch (pci_device.class_code())
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{
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case 0x01:
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{
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switch (pci_device.subclass())
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{
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case 0x01:
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case 0x05:
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case 0x06:
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if (auto res = ATAController::create(pci_device); res.is_error())
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dprintln("ATA: {}", res.error());
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break;
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case 0x08:
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if (auto res = NVMeController::create(pci_device); res.is_error())
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dprintln("NVMe: {}", res.error());
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break;
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default:
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dprintln("unsupported storage device (pci {2H}.{2H}.{2H})", pci_device.class_code(), pci_device.subclass(), pci_device.prog_if());
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break;
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}
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break;
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}
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case 0x02:
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{
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if (auto res = NetworkManager::get().add_interface(pci_device); res.is_error())
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dprintln("{}", res.error());
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break;
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}
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default:
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break;
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}
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}
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}
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BAN::ErrorOr<BAN::UniqPtr<BarRegion>> BarRegion::create(PCI::Device& device, uint8_t bar_num)
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{
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if (device.header_type() != 0x00)
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{
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dprintln("BAR regions for non general devices are not supported");
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return BAN::Error::from_errno(ENOTSUP);
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}
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// disable io/mem space while reading bar
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uint16_t command = device.read_word(PCI_REG_COMMAND);
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device.write_word(PCI_REG_COMMAND, command & ~(PCI_CMD_IO_SPACE | PCI_CMD_MEM_SPACE));
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uint8_t offset = 0x10 + bar_num * 4;
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uint64_t addr = device.read_dword(offset);
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device.write_dword(offset, 0xFFFFFFFF);
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uint32_t size = device.read_dword(offset);
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size = ~size + 1;
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device.write_dword(offset, addr);
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// determine bar type
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BarType type = BarType::INVALID;
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if (addr & 1)
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{
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type = BarType::IO;
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addr &= 0xFFFFFFFC;
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}
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else if ((addr & 0b110) == 0b000)
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{
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type = BarType::MEM;
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addr &= 0xFFFFFFF0;
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}
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else if ((addr & 0b110) == 0b100)
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{
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type = BarType::MEM;
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addr &= 0xFFFFFFF0;
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addr |= (uint64_t)device.read_dword(offset + 4) << 32;
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}
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if (type == BarType::INVALID)
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{
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dwarnln("invalid pci device bar");
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return BAN::Error::from_errno(EINVAL);
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}
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auto* region_ptr = new BarRegion(type, addr, size);
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ASSERT(region_ptr);
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auto region = BAN::UniqPtr<BarRegion>::adopt(region_ptr);
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TRY(region->initialize());
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// restore old command register and enable correct IO/MEM space
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command |= (type == BarType::IO) ? PCI_CMD_IO_SPACE : PCI_CMD_MEM_SPACE;
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device.write_word(PCI_REG_COMMAND, command);
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#if DEBUG_PCI
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dprintln("created BAR region for PCI {2H}:{2H}.{2H}",
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device.bus(),
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device.dev(),
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device.func()
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);
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dprintln(" type: {}", region->type() == BarType::IO ? "IO" : "MEM");
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if (region->type() == BarType::IO)
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dprintln(" iobase {8H}", region->iobase());
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else
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{
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dprintln(" paddr {}", (void*)region->paddr());
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dprintln(" vaddr {}", (void*)region->vaddr());
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}
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dprintln(" size {}", region->size());
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#endif
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return region;
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}
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BarRegion::BarRegion(BarType type, paddr_t paddr, size_t size)
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: m_type(type)
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, m_paddr(paddr)
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, m_size(size)
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{ }
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BarRegion::~BarRegion()
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{
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if (m_type == BarType::MEM && m_vaddr)
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PageTable::kernel().unmap_range(m_vaddr, m_size);
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m_vaddr = 0;
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}
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BAN::ErrorOr<void> BarRegion::initialize()
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{
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if (m_type == BarType::IO)
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return {};
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size_t needed_pages = BAN::Math::div_round_up<size_t>(m_size, PAGE_SIZE);
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m_vaddr = PageTable::kernel().reserve_free_contiguous_pages(needed_pages, KERNEL_OFFSET);
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if (m_vaddr == 0)
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return BAN::Error::from_errno(ENOMEM);
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PageTable::kernel().map_range_at(m_paddr, m_vaddr, m_size, PageTable::Flags::CacheDisable | PageTable::Flags::ReadWrite | PageTable::Flags::Present);
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return {};
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}
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void BarRegion::write8(off_t reg, uint8_t val)
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{
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if (m_type == BarType::IO)
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return IO::outb(m_paddr + reg, val);
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MMIO::write8(m_vaddr + reg, val);
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}
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void BarRegion::write16(off_t reg, uint16_t val)
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{
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if (m_type == BarType::IO)
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return IO::outw(m_paddr + reg, val);
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MMIO::write16(m_vaddr + reg, val);
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}
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void BarRegion::write32(off_t reg, uint32_t val)
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{
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if (m_type == BarType::IO)
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return IO::outl(m_paddr + reg, val);
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MMIO::write32(m_vaddr + reg, val);
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}
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uint8_t BarRegion::read8(off_t reg)
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{
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if (m_type == BarType::IO)
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return IO::inb(m_paddr + reg);
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return MMIO::read8(m_vaddr + reg);
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}
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uint16_t BarRegion::read16(off_t reg)
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{
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if (m_type == BarType::IO)
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return IO::inw(m_paddr + reg);
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return MMIO::read16(m_vaddr + reg);
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}
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uint32_t BarRegion::read32(off_t reg)
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{
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if (m_type == BarType::IO)
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return IO::inl(m_paddr + reg);
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return MMIO::read32(m_vaddr + reg);
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}
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PCI::Device::Device(uint8_t bus, uint8_t dev, uint8_t func)
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: m_bus(bus), m_dev(dev), m_func(func)
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{
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uint32_t type = read_word(0x0A);
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m_class_code = (uint8_t)(type >> 8);
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m_subclass = (uint8_t)(type);
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m_prog_if = read_byte(0x09);
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m_header_type = read_byte(0x0E);
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uint32_t device = read_dword(0x00);
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m_vendor_id = device & 0xFFFF;
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m_device_id = device >> 16;
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dprintln("PCI {2H}:{2H}.{2H} has {2H}.{2H}.{2H}",
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m_bus, m_dev, m_func,
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m_class_code, m_subclass, m_prog_if
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);
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enumerate_capabilites();
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}
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uint32_t PCI::Device::read_dword(uint8_t offset) const
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{
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ASSERT(offset % 4 == 0);
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return PCIManager::read_config_dword(m_bus, m_dev, m_func, offset);
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}
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uint16_t PCI::Device::read_word(uint8_t offset) const
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{
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ASSERT(offset % 2 == 0);
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return PCIManager::read_config_word(m_bus, m_dev, m_func, offset);
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}
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uint8_t PCI::Device::read_byte(uint8_t offset) const
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{
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return PCIManager::read_config_byte(m_bus, m_dev, m_func, offset);
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}
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void PCI::Device::write_dword(uint8_t offset, uint32_t value)
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{
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ASSERT(offset % 4 == 0);
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PCIManager::write_config_dword(m_bus, m_dev, m_func, offset, value);
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}
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void PCI::Device::write_word(uint8_t offset, uint16_t value)
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{
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ASSERT(offset % 2 == 0);
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PCIManager::write_config_word(m_bus, m_dev, m_func, offset, value);
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}
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void PCI::Device::write_byte(uint8_t offset, uint8_t value)
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{
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PCIManager::write_config_byte(m_bus, m_dev, m_func, offset, value);
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}
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BAN::ErrorOr<BAN::UniqPtr<BarRegion>> PCI::Device::allocate_bar_region(uint8_t bar_num)
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{
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return BarRegion::create(*this, bar_num);
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}
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void PCI::Device::enumerate_capabilites()
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{
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uint16_t status = read_word(PCI_REG_STATUS);
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if (!(status & (1 << 4)))
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return;
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uint8_t capability_offset = read_byte(PCI_REG_CAPABILITIES) & 0xFC;
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while (capability_offset)
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{
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uint16_t capability_info = read_word(capability_offset);
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switch (capability_info & 0xFF)
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{
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case 0x05:
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m_offset_msi = capability_offset;
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break;
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case 0x11:
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m_offset_msi_x = capability_offset;
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break;
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default:
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break;
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}
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capability_offset = (capability_info >> 8) & 0xFC;
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}
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}
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BAN::ErrorOr<void> PCI::Device::reserve_irqs(uint8_t count)
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{
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if (m_offset_msi_x.has_value())
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{
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uint16_t msg_ctrl = read_word(*m_offset_msi_x + 0x02);
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if (count > (msg_ctrl & 0x7FF) + 1)
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{
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dwarnln("MSI-X: could not allocate {} interrupts, only {} supported", count, (msg_ctrl & 0x7FF) + 1);
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return BAN::Error::from_errno(EFAULT);
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}
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msg_ctrl |= 1 << 15; // Enable
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write_word(*m_offset_msi_x + 0x02, msg_ctrl);
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disable_pin_interrupts();
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}
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else if (m_offset_msi.has_value())
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{
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if (count > 1)
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{
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dwarnln("MSI: could not allocate {} interrupts, (currently) only {} supported", count, 1);
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return BAN::Error::from_errno(EFAULT);
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}
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uint16_t msg_ctrl = read_word(*m_offset_msi + 0x02);
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msg_ctrl &= ~(0x07 << 4); // Only one interrupt
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msg_ctrl |= 1u << 0; // Enable
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write_word(*m_offset_msi + 0x02, msg_ctrl);
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disable_pin_interrupts();
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}
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else if (!InterruptController::get().is_using_apic())
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{
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if (count > 1)
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{
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dwarnln("PIC: could not allocate {} interrupts, (currently) only {} supported", count, 1);
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return BAN::Error::from_errno(EFAULT);
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}
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enable_pin_interrupts();
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}
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else
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{
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dwarnln("Could not reserve interrupt for PCI device. No MSI, MSI-X or interrupt line is used");
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return BAN::Error::from_errno(EFAULT);
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}
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for (; m_reserved_irq_count < count; m_reserved_irq_count++)
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{
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auto irq = InterruptController::get().get_free_irq();
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if (!irq.has_value())
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{
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dwarnln("Could not reserve interrupt for PCI {}:{}.{}", m_bus, m_dev, m_func);
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return BAN::Error::from_errno(EFAULT);
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}
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ASSERT(*irq < 32);
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ASSERT(!(m_reserved_irqs & (1 << *irq)));
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m_reserved_irqs |= 1 << *irq;
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}
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return {};
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}
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static constexpr uint64_t msi_message_address()
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{
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return 0xFEE00000;
|
|
}
|
|
|
|
static constexpr uint32_t msi_message_data(uint8_t irq)
|
|
{
|
|
return (IRQ_VECTOR_BASE + irq) & 0xFF;
|
|
}
|
|
|
|
uint8_t PCI::Device::get_irq(uint8_t index)
|
|
{
|
|
ASSERT(m_offset_msi.has_value() || m_offset_msi_x.has_value() || !InterruptController::get().is_using_apic());
|
|
ASSERT(index < m_reserved_irq_count);
|
|
|
|
uint8_t count_found = 0;
|
|
uint8_t irq = 0xFF;
|
|
for (uint8_t i = 0; i < 32; i++)
|
|
{
|
|
if (m_reserved_irqs & (1 << i))
|
|
count_found++;
|
|
if (count_found > index)
|
|
{
|
|
irq = i;
|
|
break;
|
|
}
|
|
}
|
|
ASSERT(irq != 0xFF);
|
|
|
|
// Legacy PIC just uses the interrupt line field
|
|
if (!InterruptController::get().is_using_apic())
|
|
{
|
|
write_byte(PCI_REG_IRQ_LINE, irq);
|
|
return irq;
|
|
}
|
|
|
|
if (m_offset_msi_x.has_value())
|
|
{
|
|
uint32_t dword0 = read_dword(*m_offset_msi_x);
|
|
ASSERT((dword0 & 0xFF) == 0x11);
|
|
|
|
uint32_t dword1 = read_dword(*m_offset_msi_x + 0x04);
|
|
uint32_t offset = dword1 & ~3u;
|
|
uint8_t bir = dword1 & 3u;
|
|
|
|
uint64_t msg_addr = msi_message_address();
|
|
uint32_t msg_data = msi_message_data(irq);
|
|
|
|
auto bar = MUST(allocate_bar_region(bir));
|
|
ASSERT(bar->type() == BarType::MEM);
|
|
auto& msi_x_entry = reinterpret_cast<volatile MSIXEntry*>(bar->vaddr() + offset)[index];
|
|
msi_x_entry.msg_addr_low = msg_addr & 0xFFFFFFFF;
|
|
msi_x_entry.msg_addr_high = msg_addr >> 32;;
|
|
msi_x_entry.msg_data = msg_data;
|
|
msi_x_entry.vector_ctrl = msi_x_entry.vector_ctrl & ~1u;
|
|
|
|
return irq;
|
|
}
|
|
|
|
if (m_offset_msi.has_value())
|
|
{
|
|
uint32_t dword0 = read_dword(*m_offset_msi);
|
|
ASSERT((dword0 & 0xFF) == 0x05);
|
|
|
|
uint64_t msg_addr = msi_message_address();
|
|
uint32_t msg_data = msi_message_data(irq);
|
|
|
|
if (dword0 & (1 << 23))
|
|
{
|
|
write_dword(*m_offset_msi + 0x04, msg_addr & 0xFFFFFFFF);
|
|
write_dword(*m_offset_msi + 0x08, msg_addr >> 32);
|
|
write_word(*m_offset_msi + 0x12, msg_data);
|
|
}
|
|
else
|
|
{
|
|
write_dword(*m_offset_msi + 0x04, msg_addr & 0xFFFFFFFF);
|
|
write_word(*m_offset_msi + 0x08, msg_data);
|
|
}
|
|
|
|
return irq;
|
|
}
|
|
|
|
ASSERT_NOT_REACHED();
|
|
}
|
|
|
|
void PCI::Device::set_command_bits(uint16_t mask)
|
|
{
|
|
write_dword(PCI_REG_COMMAND, read_dword(PCI_REG_COMMAND) | mask);
|
|
}
|
|
|
|
void PCI::Device::unset_command_bits(uint16_t mask)
|
|
{
|
|
write_dword(PCI_REG_COMMAND, read_dword(PCI_REG_COMMAND) & ~mask);
|
|
}
|
|
|
|
void PCI::Device::enable_bus_mastering()
|
|
{
|
|
set_command_bits(PCI_CMD_BUS_MASTER);
|
|
}
|
|
|
|
void PCI::Device::disable_bus_mastering()
|
|
{
|
|
unset_command_bits(PCI_CMD_BUS_MASTER);
|
|
}
|
|
|
|
void PCI::Device::enable_memory_space()
|
|
{
|
|
set_command_bits(PCI_CMD_MEM_SPACE);
|
|
}
|
|
|
|
void PCI::Device::disable_memory_space()
|
|
{
|
|
unset_command_bits(PCI_CMD_MEM_SPACE);
|
|
}
|
|
|
|
void PCI::Device::enable_io_space()
|
|
{
|
|
set_command_bits(PCI_CMD_IO_SPACE);
|
|
}
|
|
|
|
void PCI::Device::disable_io_space()
|
|
{
|
|
unset_command_bits(PCI_CMD_IO_SPACE);
|
|
}
|
|
|
|
void PCI::Device::enable_pin_interrupts()
|
|
{
|
|
unset_command_bits(PCI_CMD_INTERRUPT_DISABLE);
|
|
}
|
|
|
|
void PCI::Device::disable_pin_interrupts()
|
|
{
|
|
set_command_bits(PCI_CMD_INTERRUPT_DISABLE);
|
|
}
|
|
|
|
}
|