Bananymous
2d11ce9669
I had not understood how MSIs work and I was unnecessarily routing them through IOAPIC. This is not necessary and should not be done :D Also MSIs were reserving interrupts that IOAPIC was capable of generating. Now IOAPIC and MSIs use different set of interrupts so IOAPIC can use more interrupts if needed.
90 lines
1.7 KiB
C++
90 lines
1.7 KiB
C++
#pragma once
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#include <BAN/Array.h>
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#include <BAN/NoCopyMove.h>
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#include <kernel/Arch.h>
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#include <kernel/Interruptable.h>
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#include <stdint.h>
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namespace Kernel
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{
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// IDT entries
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// 0x00->0x1F (32): ISR
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// 0x20->0x7F (96): PIC/IOAPIC
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// 0x80->0xEF (112): MSI
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// 0xF0->0xFE (15): internal
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constexpr uint8_t IRQ_VECTOR_BASE = 0x20;
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constexpr uint8_t IRQ_MSI_BASE = 0x80;
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constexpr uint8_t IRQ_SYSCALL = 0xF0;
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constexpr uint8_t IRQ_YIELD = 0xF1;
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constexpr uint8_t IRQ_IPI = 0xF2;
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constexpr uint8_t IRQ_TIMER = 0xF3;
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#if ARCH(x86_64)
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struct GateDescriptor
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{
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uint16_t offset0;
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uint16_t selector;
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uint8_t IST;
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uint8_t flags;
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uint16_t offset1;
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uint32_t offset2;
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uint32_t reserved;
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};
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static_assert(sizeof(GateDescriptor) == 16);
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#elif ARCH(i686)
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struct GateDescriptor
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{
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uint16_t offset0;
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uint16_t selector;
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uint8_t reserved;
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uint8_t flags;
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uint16_t offset1;
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};
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static_assert(sizeof(GateDescriptor) == 8);
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#else
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#error
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#endif
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struct IDTR
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{
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uint16_t size;
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uintptr_t offset;
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} __attribute__((packed));
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class IDT
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{
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BAN_NON_COPYABLE(IDT);
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BAN_NON_MOVABLE(IDT);
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public:
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static IDT* create();
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[[noreturn]] static void force_triple_fault();
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void register_irq_handler(uint8_t irq, Interruptable* interruptable);
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void load()
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{
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asm volatile("lidt %0" :: "m"(m_idtr) : "memory");
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}
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private:
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IDT() = default;
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void register_interrupt_handler(uint8_t index, void (*handler)());
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void register_syscall_handler(uint8_t index, void (*handler)());
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private:
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BAN::Array<GateDescriptor, 0x100> m_idt;
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IDTR m_idtr {
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.size = static_cast<uint16_t>(m_idt.size() * sizeof(GateDescriptor) - 1),
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.offset = reinterpret_cast<uintptr_t>(m_idt.data())
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};
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};
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}
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