Bananymous
6339044e4c
This now works properly on real hardware. Main issue was a race condition with now ISR was handled in the interrupt handler. We now loop until we read back ISR as zero
341 lines
10 KiB
C++
341 lines
10 KiB
C++
#include <kernel/Lock/SpinLockAsMutex.h>
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#include <kernel/Networking/NetworkManager.h>
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#include <kernel/Networking/RTL8169/Definitions.h>
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#include <kernel/Networking/RTL8169/RTL8169.h>
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#include <kernel/Timer/Timer.h>
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namespace Kernel
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{
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// each buffer is 7440 bytes + padding = 8192
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constexpr size_t s_buffer_size = 8192;
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bool RTL8169::probe(PCI::Device& pci_device)
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{
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if (pci_device.vendor_id() != 0x10ec)
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return false;
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switch (pci_device.device_id())
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{
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case 0x8161:
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case 0x8168:
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case 0x8169:
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return true;
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default:
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return false;
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}
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}
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BAN::ErrorOr<BAN::RefPtr<RTL8169>> RTL8169::create(PCI::Device& pci_device)
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{
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auto rtl8169 = TRY(BAN::RefPtr<RTL8169>::create(pci_device));
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TRY(rtl8169->initialize());
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return rtl8169;
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}
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BAN::ErrorOr<void> RTL8169::initialize()
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{
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m_pci_device.enable_bus_mastering();
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m_io_bar_region = TRY(m_pci_device.allocate_bar_region(0));
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if (m_io_bar_region->type() != PCI::BarType::IO)
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{
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dwarnln("RTL8169 BAR0 is not IO space");
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return BAN::Error::from_errno(EINVAL);
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}
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dprintln("Initializing RTL8169");
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TRY(reset());
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// disable rx, tx, checksum offload
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m_io_bar_region->write16(RTL8169_IO_CPlusCR, 0x0000);
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m_io_bar_region->write8 (RTL8169_IO_CR, 0x00);
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dprintln(" reset done");
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for (size_t i = 0; i < 6; i++)
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m_mac_address.address[i] = m_io_bar_region->read8(RTL8169_IO_IDR0 + i);
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dprintln(" MAC {}", m_mac_address);
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TRY(initialize_rx());
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TRY(initialize_tx());
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m_io_bar_region->write8(RTL8169_IO_CR, RTL8169_CR_RE | RTL8169_CR_TE);
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dprintln(" descriptors initialized");
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m_link_up = m_io_bar_region->read8(RTL8169_IO_PHYSts) & RTL8169_PHYSts_LinkSts;
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dprintln(" link status {}", link_up() ? "UP" : "DOWN");
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if (link_up())
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dprintln(" link speed {}", link_speed());
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TRY(enable_interrupt());
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dprintln(" interrupts enabled");
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auto* thread = TRY(Thread::create_kernel([](void* rtl8169_ptr) {
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static_cast<RTL8169*>(rtl8169_ptr)->receive_thread();
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}, this));
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if (auto ret = Processor::scheduler().add_thread(thread); ret.is_error())
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{
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delete thread;
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return ret.release_error();
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}
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m_rx_thread_is_dead = false;
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return {};
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}
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RTL8169::~RTL8169()
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{
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m_rx_thread_should_die = true;
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m_rx_blocker.unblock();
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while (!m_rx_thread_is_dead)
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Processor::yield();
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}
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BAN::ErrorOr<void> RTL8169::reset()
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{
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m_io_bar_region->write8(RTL8169_IO_CR, RTL8169_CR_RST);
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const uint64_t timeout_ms = SystemTimer::get().ms_since_boot() + 100;
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while (m_io_bar_region->read8(RTL8169_IO_CR) & RTL8169_CR_RST)
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if (SystemTimer::get().ms_since_boot() >= timeout_ms)
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return BAN::Error::from_errno(ETIMEDOUT);
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return {};
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}
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BAN::ErrorOr<void> RTL8169::initialize_rx()
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{
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m_rx_buffer_region = TRY(DMARegion::create(m_rx_descriptor_count * s_buffer_size, PageTable::MemoryType::Normal));
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m_rx_descriptor_region = TRY(DMARegion::create(m_rx_descriptor_count * sizeof(RTL8169Descriptor)));
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auto* rx_descriptors = reinterpret_cast<volatile RTL8169Descriptor*>(m_rx_descriptor_region->vaddr());
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for (size_t i = 0; i < m_rx_descriptor_count; i++)
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{
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const paddr_t rx_buffer_paddr = m_rx_buffer_region->paddr() + i * s_buffer_size;
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rx_descriptors[i].command = 0x1FF8 | RTL8169_DESC_CMD_OWN;
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rx_descriptors[i].vlan = 0;
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rx_descriptors[i].buffer_low = rx_buffer_paddr & 0xFFFFFFFF;
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rx_descriptors[i].buffer_high = rx_buffer_paddr >> 32;
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}
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rx_descriptors[m_rx_descriptor_count - 1].command |= RTL8169_DESC_CMD_EOR;
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// configure rx descriptor addresses
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m_io_bar_region->write32(RTL8169_IO_RDSAR + 4, m_rx_descriptor_region->paddr() >> 32);
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m_io_bar_region->write32(RTL8169_IO_RDSAR + 0, m_rx_descriptor_region->paddr() & 0xFFFFFFFF);
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// configure receive control (no fifo threshold, max dma burst unlimited, broadcast, multicast, accept physical match)
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m_io_bar_region->write32(RTL8169_IO_RCR,
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RTL8169_RCR_RXFTH_NO | RTL8169_RCR_MXDMA_UNLIMITED | RTL8169_RCR_AB | RTL8169_RCR_AM | RTL8169_RCR_APM
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);
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// configure max rx packet size
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m_io_bar_region->write16(RTL8169_IO_RMS, RTL8169_RMS_MAX);
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return {};
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}
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BAN::ErrorOr<void> RTL8169::initialize_tx()
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{
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m_tx_buffer_region = TRY(DMARegion::create(m_tx_descriptor_count * s_buffer_size, PageTable::MemoryType::Normal));
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m_tx_descriptor_region = TRY(DMARegion::create(m_tx_descriptor_count * sizeof(RTL8169Descriptor)));
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auto* tx_descriptors = reinterpret_cast<volatile RTL8169Descriptor*>(m_tx_descriptor_region->vaddr());
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for (size_t i = 0; i < m_tx_descriptor_count; i++)
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{
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const paddr_t tx_buffer_paddr = m_tx_buffer_region->paddr() + i * s_buffer_size;
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tx_descriptors[i].command = 0;
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tx_descriptors[i].vlan = 0;
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tx_descriptors[i].buffer_low = tx_buffer_paddr & 0xFFFFFFFF;
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tx_descriptors[i].buffer_high = tx_buffer_paddr >> 32;
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}
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tx_descriptors[m_tx_descriptor_count - 1].command |= RTL8169_DESC_CMD_EOR;
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// configure tx descriptor addresses
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m_io_bar_region->write32(RTL8169_IO_TNPDS + 4, m_tx_descriptor_region->paddr() >> 32);
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m_io_bar_region->write32(RTL8169_IO_TNPDS + 0, m_tx_descriptor_region->paddr() & 0xFFFFFFFF);
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// configure transmit control (standard ifg, max dma burst unlimited)
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m_io_bar_region->write32(RTL8169_IO_TCR, RTL8169_TCR_IFG_0 | RTL8169_TCR_MXDMA_UNLIMITED);
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// configure max tx packet size
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m_io_bar_region->write8(RTL8169_IO_MTPS, RTL8169_MTPS_MAX);
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return {};
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}
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BAN::ErrorOr<void> RTL8169::enable_interrupt()
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{
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TRY(m_pci_device.reserve_interrupts(1));
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m_pci_device.enable_interrupt(0, *this);
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m_io_bar_region->write16(RTL8169_IO_IMR,
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RTL8169_IR_ROK |
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RTL8169_IR_RER |
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RTL8169_IR_TOK |
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RTL8169_IR_TER |
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RTL8169_IR_RDU |
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RTL8169_IR_LinkChg |
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RTL8169_IR_FVOW
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);
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m_io_bar_region->write16(RTL8169_IO_ISR, 0xFFFF);
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return {};
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}
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int RTL8169::link_speed()
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{
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if (!link_up())
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return 0;
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const uint8_t phy_status = m_io_bar_region->read8(RTL8169_IO_PHYSts);
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if (phy_status & RTL8169_PHYSts_1000MF)
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return 1000;
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if (phy_status & RTL8169_PHYSts_100M)
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return 100;
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if (phy_status & RTL8169_PHYSts_10M)
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return 10;
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return 0;
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}
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BAN::ErrorOr<void> RTL8169::send_bytes(BAN::MACAddress destination, EtherType protocol, BAN::Span<const BAN::ConstByteSpan> payload)
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{
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if (!link_up())
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return BAN::Error::from_errno(EADDRNOTAVAIL);
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const auto interrupt_state = Processor::get_interrupt_state();
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Processor::set_interrupt_state(InterruptState::Disabled);
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const uint32_t tx_current_nowrap = m_tx_head.fetch_add(1);
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const uint32_t tx_current = tx_current_nowrap % m_tx_descriptor_count;
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auto& descriptor = reinterpret_cast<volatile RTL8169Descriptor*>(m_tx_descriptor_region->vaddr())[tx_current];
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if (descriptor.command & RTL8169_DESC_CMD_OWN)
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{
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SpinLockGuard guard(m_tx_lock);
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while (descriptor.command & RTL8169_DESC_CMD_OWN)
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{
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SpinLockGuardAsMutex smutex(guard);
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m_tx_blocker.block_indefinite(&smutex);
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}
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}
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auto* tx_buffer = reinterpret_cast<uint8_t*>(m_tx_buffer_region->vaddr() + tx_current * s_buffer_size);
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// write packet
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auto& ethernet_header = *reinterpret_cast<EthernetHeader*>(tx_buffer);
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ethernet_header.dst_mac = destination;
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ethernet_header.src_mac = get_mac_address();
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ethernet_header.ether_type = protocol;
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size_t packet_size = sizeof(EthernetHeader);
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for (const auto& buffer : payload)
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{
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memcpy(tx_buffer + packet_size, buffer.data(), buffer.size());
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packet_size += buffer.size();
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}
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// give packet ownership to NIC
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uint32_t command = packet_size | RTL8169_DESC_CMD_OWN | RTL8169_DESC_CMD_LS | RTL8169_DESC_CMD_FS;
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if (tx_current == m_tx_descriptor_count - 1)
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command |= RTL8169_DESC_CMD_EOR;
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descriptor.command = command;
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// ring tx queue doorbell
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if (tx_current_nowrap == m_tx_commit.load())
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m_io_bar_region->write8(RTL8169_IO_TPPoll, RTL8169_TPPoll_NPQ);
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while (tx_current_nowrap != m_tx_commit.load())
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Processor::pause();
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m_tx_commit.add_fetch(1);
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Processor::set_interrupt_state(interrupt_state);
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return {};
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}
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void RTL8169::receive_thread()
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{
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SpinLockGuard rx_lock_guard(m_rx_lock);
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while (!m_rx_thread_should_die)
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{
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for (;;)
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{
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auto& descriptor = reinterpret_cast<volatile RTL8169Descriptor*>(m_rx_descriptor_region->vaddr())[m_rx_head];
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if (descriptor.command & RTL8169_DESC_CMD_OWN)
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break;
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// packet buffer can only hold single packet, so we should not receive any multi-descriptor packets
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ASSERT((descriptor.command & RTL8169_DESC_CMD_LS) && (descriptor.command & RTL8169_DESC_CMD_FS));
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const uint16_t packet_length = descriptor.command & 0x3FFF;
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if (packet_length > s_buffer_size)
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dwarnln("Got {} bytes to {} byte buffer", packet_length, s_buffer_size);
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else if (descriptor.command & (1u << 21))
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; // descriptor has an error
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else
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{
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m_rx_lock.unlock(InterruptState::Enabled);
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NetworkManager::get().on_receive(*this, BAN::ConstByteSpan {
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reinterpret_cast<const uint8_t*>(m_rx_buffer_region->vaddr() + m_rx_head * s_buffer_size),
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packet_length
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});
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m_rx_lock.lock();
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}
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uint32_t command = 0x1FF8 | RTL8169_DESC_CMD_OWN;
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if (m_rx_head == m_rx_descriptor_count - 1)
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command |= RTL8169_DESC_CMD_EOR;
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descriptor.command = command;
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m_rx_head = (m_rx_head + 1) % m_rx_descriptor_count;
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}
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SpinLockGuardAsMutex smutex(rx_lock_guard);
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m_rx_blocker.block_indefinite(&smutex);
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}
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m_rx_thread_is_dead = true;
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}
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void RTL8169::handle_irq()
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{
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uint16_t isr;
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while ((isr = m_io_bar_region->read16(RTL8169_IO_ISR)))
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{
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m_io_bar_region->write16(RTL8169_IO_ISR, isr);
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if (isr & RTL8169_IR_LinkChg)
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{
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m_link_up = m_io_bar_region->read8(RTL8169_IO_PHYSts) & RTL8169_PHYSts_LinkSts;
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dprintln("link status {}", link_up() ? "UP" : "DOWN");
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if (link_up())
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dprintln("link speed {}", link_speed());
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}
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if (isr & (RTL8169_IR_TER | RTL8169_IR_TOK))
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{
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SpinLockGuard _(m_tx_lock);
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m_tx_blocker.unblock();
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}
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if (isr & (RTL8169_IR_RER | RTL8169_IR_ROK))
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{
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SpinLockGuard _(m_rx_lock);
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m_rx_blocker.unblock();
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}
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if (isr & RTL8169_IR_RER)
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dwarnln("Rx error");
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if (isr & RTL8169_IR_TER)
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dwarnln("Tx error");
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if (isr & RTL8169_IR_RDU)
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dwarnln("Rx descriptor not available");
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if (isr & RTL8169_IR_FVOW)
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dwarnln("Rx FIFO overflow");
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}
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}
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}
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