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base: Bananymous:539afb329a2936b1bf51be56efc246c5c97df90d
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compare: Bananymous:9548c592a3af8b12bf23f1cb7fe60b62fbbd0500
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Bananymous:main

2 Commits
539afb329a ... 9548c592a3

Author SHA1 Message Date
Bananymous 9548c592a3 Kernel: Always print basic info about xHCI controller 
Its nice to see that the controller is getting initalized
 2024-07-23 09:09:08 +03:00
Bananymous cda0276d39 Kernel: Force PCI irq line usage when not using APIC 
afaik PIC does not support MSI
 2024-07-23 09:08:00 +03:00
3 changed files with 16 additions and 16 deletions
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2
kernel/include/kernel/PIC.h
View File

@ -29,7 +29,7 @@ namespace Kernel
private: private:
SpinLock m_lock; SpinLock m_lock;
uint16_t m_reserved_irqs { 0 }; uint16_t m_reserved_irqs { 1u << 2 };
friend class InterruptController; friend class InterruptController;
}; };

20
kernel/kernel/PCI.cpp
View File

@ -362,7 +362,16 @@ namespace Kernel::PCI
BAN::ErrorOr<void> PCI::Device::reserve_irqs(uint8_t count) BAN::ErrorOr<void> PCI::Device::reserve_irqs(uint8_t count)
{ {
if (m_offset_msi_x.has_value()) if (!InterruptController::get().is_using_apic())
{
if (count > 1)
{
dwarnln("PIC: could not allocate {} interrupts, (currently) only {} supported", count, 1);
return BAN::Error::from_errno(EFAULT);
}
enable_pin_interrupts();
}
else if (m_offset_msi_x.has_value())
{ {
uint16_t msg_ctrl = read_word(*m_offset_msi_x + 0x02); uint16_t msg_ctrl = read_word(*m_offset_msi_x + 0x02);
if (count > (msg_ctrl & 0x7FF) + 1) if (count > (msg_ctrl & 0x7FF) + 1)
@ -387,15 +396,6 @@ namespace Kernel::PCI
write_word(*m_offset_msi + 0x02, msg_ctrl); write_word(*m_offset_msi + 0x02, msg_ctrl);
disable_pin_interrupts(); disable_pin_interrupts();
} }
else if (!InterruptController::get().is_using_apic())
{
if (count > 1)
{
dwarnln("PIC: could not allocate {} interrupts, (currently) only {} supported", count, 1);
return BAN::Error::from_errno(EFAULT);
}
enable_pin_interrupts();
}
else else
{ {
dwarnln("Could not reserve interrupt for PCI device. No MSI, MSI-X or interrupt line is used"); dwarnln("Could not reserve interrupt for PCI device. No MSI, MSI-X or interrupt line is used");

10
kernel/kernel/USB/XHCI/Controller.cpp
View File

@ -75,7 +75,7 @@ namespace Kernel
BAN::ErrorOr<void> XHCIController::initialize_impl() BAN::ErrorOr<void> XHCIController::initialize_impl()
{ {
dprintln_if(DEBUG_XHCI, "XHCI controller at PCI {2H}:{2H}:{2H}", m_pci_device.bus(), m_pci_device.dev(), m_pci_device.func()); dprintln("XHCI controller at PCI {2H}:{2H}:{2H}", m_pci_device.bus(), m_pci_device.dev(), m_pci_device.func());
m_pci_device.enable_bus_mastering(); m_pci_device.enable_bus_mastering();
m_pci_device.enable_memory_space(); m_pci_device.enable_memory_space();
@ -94,14 +94,14 @@ namespace Kernel
} }
auto& capabilities = capability_regs(); auto& capabilities = capability_regs();
dprintln_if(DEBUG_XHCI, " version {H}.{H}.{H}", dprintln(" version {H}.{H}.{H}",
+capabilities.major_revision, +capabilities.major_revision,
capabilities.minor_revision >> 4, capabilities.minor_revision >> 4,
capabilities.minor_revision & 0x0F capabilities.minor_revision & 0x0F
); );
dprintln_if(DEBUG_XHCI, " max slots {}", +capabilities.hcsparams1.max_slots); dprintln(" max slots {}", +capabilities.hcsparams1.max_slots);
dprintln_if(DEBUG_XHCI, " max intrs {}", +capabilities.hcsparams1.max_interrupters); dprintln(" max intrs {}", +capabilities.hcsparams1.max_interrupters);
dprintln_if(DEBUG_XHCI, " max ports {}", +capabilities.hcsparams1.max_ports); dprintln(" max ports {}", +capabilities.hcsparams1.max_ports);
TRY(m_slots.resize(capabilities.hcsparams1.max_slots)); TRY(m_slots.resize(capabilities.hcsparams1.max_slots));
TRY(m_ports.resize(capabilities.hcsparams1.max_ports)); TRY(m_ports.resize(capabilities.hcsparams1.max_ports));