Kernel: I have no idea what this commit does
I had committed a change in IDT but reverted it now. This propably only adds a spurious interrupt detection to common cpp interrupt handler?
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@ -137,7 +137,19 @@ namespace IDT
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if (s_irq_handlers[irq])
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s_irq_handlers[irq]();
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else
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Kernel::Panic("no handler for irq 0x{2H}\n", irq);
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{
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uint32_t isr_byte = irq / 32;
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uint32_t isr_bit = irq % 32;
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uint32_t isr[8];
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InterruptController::Get().GetISR(isr);
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if (!(isr[isr_byte] & (1 << isr_bit)))
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{
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dprintln("spurious irq 0x{2H}", irq);
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return;
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}
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dprintln("no handler for irq 0x{2H}\n", irq);
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}
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InterruptController::Get().EOI(irq);
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}
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@ -95,7 +95,19 @@ namespace IDT
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if (s_irq_handlers[irq])
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s_irq_handlers[irq]();
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else
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{
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uint32_t isr_byte = irq / 32;
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uint32_t isr_bit = irq % 32;
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uint32_t isr[8];
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InterruptController::Get().GetISR(isr);
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if (!(isr[isr_byte] & (1 << isr_bit)))
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{
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dprintln("spurious irq 0x{2H}", irq);
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return;
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}
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dprintln("no handler for irq 0x{2H}\n", irq);
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}
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InterruptController::Get().EOI(irq);
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}
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@ -11,7 +11,8 @@
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#define PIC2_COMMAND PIC2
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#define PIC2_DATA (PIC2+1)
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#define PIC_EOI 0x20 /* End-of-interrupt command code */
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#define PIC_READ_ISR 0x0B
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#define PIC_EOI 0x20
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#define ICW1_ICW4 0x01 /* ICW4 (not) needed */
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#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
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@ -100,8 +101,8 @@ void PIC::EnableIrq(uint8_t irq)
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void PIC::GetISR(uint32_t out[8])
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{
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memset(out, 0, 8 * sizeof(uint32_t));
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IO::outb(PIC1_COMMAND, 0x0b);
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IO::outb(PIC2_COMMAND, 0x0b);
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IO::outb(PIC1_COMMAND, PIC_READ_ISR);
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IO::outb(PIC2_COMMAND, PIC_READ_ISR);
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uint16_t isr0 = IO::inb(PIC1_COMMAND);
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uint16_t isr1 = IO::inb(PIC2_COMMAND);
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