Bananymous
/
banan-os
1
1
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Kernel: NVMe Queue max simultaneous commands is dependent on arch 

This allows mask to be atomic on 32 bit architectures
This commit is contained in:
Bananymous 2024-03-26 01:45:43 +02:00
parent fc7e96fa66
commit a9db4dd9a3
2 changed files with 16 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
kernel/include/kernel/Storage/NVMe/Queue.h
View File

@ -31,11 +31,13 @@ namespace Kernel
uint32_t m_cq_head { 0 };
uint16_t m_cq_valid_phase { 1 };
Semaphore m_semaphore;
SpinLock m_lock;
BAN::Atomic<uint64_t> m_used_mask { 0 };
BAN::Atomic<uint64_t> m_done_mask { 0 };
volatile uint16_t m_status_codes[64] { };
Semaphore m_semaphore;
SpinLock m_lock;
BAN::Atomic<size_t> m_used_mask { 0 };
BAN::Atomic<size_t> m_done_mask { 0 };
volatile uint16_t m_status_codes[64] { };
static constexpr size_t m_mask_bits = sizeof(size_t) * 8;
};
}

18
kernel/kernel/Storage/NVMe/Queue.cpp
View File

@ -15,8 +15,8 @@ namespace Kernel
, m_doorbell(db)
, m_qdepth(qdepth)
{
for (uint32_t i = qdepth; i < 64; i++)
m_used_mask |= (uint64_t)1 << i;
for (uint32_t i = qdepth; i < m_mask_bits; i++)
m_used_mask |= (size_t)1 << i;
set_irq(irq);
enable_interrupt();
}
@ -29,8 +29,8 @@ namespace Kernel
{
uint16_t sts = cq_ptr[m_cq_head].sts >> 1;
uint16_t cid = cq_ptr[m_cq_head].cid;
uint64_t cid_mask = (uint64_t)1 << cid;
ASSERT(cid < 64);
size_t cid_mask = (size_t)1 << cid;
ASSERT(cid < m_mask_bits);
ASSERT((m_done_mask & cid_mask) == 0);
@ -50,7 +50,7 @@ namespace Kernel
uint16_t NVMeQueue::submit_command(NVMe::SubmissionQueueEntry& sqe)
{
uint16_t cid = reserve_cid();
uint64_t cid_mask = (uint64_t)1 << cid;
size_t cid_mask = (size_t)1 << cid;
{
SpinLockGuard _(m_lock);
@ -98,13 +98,13 @@ namespace Kernel
}
uint16_t cid = 0;
for (; cid < 64; cid++)
if ((m_used_mask & ((uint64_t)1 << cid)) == 0)
for (; cid < m_mask_bits; cid++)
if ((m_used_mask & ((size_t)1 << cid)) == 0)
break;
ASSERT(cid < 64);
ASSERT(cid < m_mask_bits);
ASSERT(cid < m_qdepth);
m_used_mask |= (uint64_t)1 << cid;
m_used_mask |= (size_t)1 << cid;
m_lock.unlock(state);
return cid;