Kernel: NVMe Queue max simultaneous commands is dependent on arch
This allows mask to be atomic on 32 bit architectures
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@@ -31,11 +31,13 @@ namespace Kernel
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uint32_t m_cq_head { 0 };
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uint16_t m_cq_valid_phase { 1 };
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Semaphore m_semaphore;
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SpinLock m_lock;
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BAN::Atomic<uint64_t> m_used_mask { 0 };
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BAN::Atomic<uint64_t> m_done_mask { 0 };
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volatile uint16_t m_status_codes[64] { };
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Semaphore m_semaphore;
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SpinLock m_lock;
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BAN::Atomic<size_t> m_used_mask { 0 };
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BAN::Atomic<size_t> m_done_mask { 0 };
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volatile uint16_t m_status_codes[64] { };
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static constexpr size_t m_mask_bits = sizeof(size_t) * 8;
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};
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}
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