Kernel: Allow Processor compilation for i386 targets
This is achieved by rewriting some inline assembly and changing ProcessorID to be 32 bit value. For some reason if processor id is 8 bits gcc runs out of 8 bit registers on i386.
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@@ -16,10 +16,10 @@ namespace Kernel
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Enabled,
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};
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using ProcessorID = uint8_t;
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constexpr ProcessorID PROCESSOR_NONE = 0xFF;
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using ProcessorID = uint32_t;
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constexpr ProcessorID PROCESSOR_NONE = 0xFFFFFFFF;
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#if ARCH(x86_64)
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#if ARCH(x86_64) || ARCH(i386)
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class Processor
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{
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BAN_NON_COPYABLE(Processor);
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@@ -75,16 +75,16 @@ namespace Kernel
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template<typename T>
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static T read_gs_sized(uintptr_t offset) requires(sizeof(T) <= 8)
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{
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#define __ASM_INPUT(operation) operation " %%gs:%a[offset], %[result]" : [result]"=r"(result) : [offset]"ir"(offset)
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#define __ASM_INPUT(operation) asm volatile(operation " %%gs:%a[offset], %[result]" : [result]"=r"(result) : [offset]"ir"(offset))
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T result;
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if constexpr(sizeof(T) == 8)
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asm volatile(__ASM_INPUT("movq"));
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__ASM_INPUT("movq");
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if constexpr(sizeof(T) == 4)
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asm volatile(__ASM_INPUT("movl"));
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__ASM_INPUT("movl");
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if constexpr(sizeof(T) == 2)
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asm volatile(__ASM_INPUT("movw"));
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__ASM_INPUT("movw");
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if constexpr(sizeof(T) == 1)
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asm volatile(__ASM_INPUT("movb"));
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__ASM_INPUT("movb");
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return result;
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#undef __ASM_INPUT
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}
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@@ -92,15 +92,15 @@ namespace Kernel
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template<typename T>
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static void write_gs_sized(uintptr_t offset, T value) requires(sizeof(T) <= 8)
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{
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#define __ASM_INPUT(operation) operation " %[value], %%gs:%a[offset]" :: [value]"r"(value), [offset]"ir"(offset) : "memory"
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#define __ASM_INPUT(operation) asm volatile(operation " %[value], %%gs:%a[offset]" :: [value]"r"(value), [offset]"ir"(offset) : "memory")
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if constexpr(sizeof(T) == 8)
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asm volatile(__ASM_INPUT("movq"));
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__ASM_INPUT("movq");
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if constexpr(sizeof(T) == 4)
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asm volatile(__ASM_INPUT("movl"));
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__ASM_INPUT("movl");
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if constexpr(sizeof(T) == 2)
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asm volatile(__ASM_INPUT("movw"));
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__ASM_INPUT("movw");
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if constexpr(sizeof(T) == 1)
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asm volatile(__ASM_INPUT("movb"));
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__ASM_INPUT("movb");
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#undef __ASM_INPUT
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}
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