Kernel: Allow HDA stream reset to timeout
This was hanging on some version of qemu :^)
This commit is contained in:
@@ -43,7 +43,7 @@ namespace Kernel
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BAN::ErrorOr<void> enable_output_path(uint8_t index);
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BAN::ErrorOr<void> enable_output_path(uint8_t index);
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BAN::ErrorOr<void> disable_output_path(uint8_t index);
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BAN::ErrorOr<void> disable_output_path(uint8_t index);
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void reset_stream();
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BAN::ErrorOr<void> reset_stream();
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BAN::ErrorOr<void> recurse_output_paths(const HDAudio::AFGWidget& widget, BAN::Vector<const HDAudio::AFGWidget*>& path);
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BAN::ErrorOr<void> recurse_output_paths(const HDAudio::AFGWidget& widget, BAN::Vector<const HDAudio::AFGWidget*>& path);
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@@ -1,6 +1,7 @@
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#include <kernel/Audio/HDAudio/AudioFunctionGroup.h>
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#include <kernel/Audio/HDAudio/AudioFunctionGroup.h>
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#include <kernel/Audio/HDAudio/Registers.h>
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#include <kernel/Audio/HDAudio/Registers.h>
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#include <kernel/FS/DevFS/FileSystem.h>
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#include <kernel/FS/DevFS/FileSystem.h>
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#include <kernel/Timer/Timer.h>
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#include <BAN/Sort.h>
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#include <BAN/Sort.h>
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@@ -202,12 +203,12 @@ namespace Kernel
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ASSERT(m_stream_index == 0xFF);
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ASSERT(m_stream_index == 0xFF);
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m_stream_index = TRY(m_controller->allocate_stream(HDAudio::StreamType::Output, this));
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m_stream_index = TRY(m_controller->allocate_stream(HDAudio::StreamType::Output, this));
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reset_stream();
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TRY(reset_stream());
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return {};
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return {};
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}
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}
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void HDAudioFunctionGroup::reset_stream()
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BAN::ErrorOr<void> HDAudioFunctionGroup::reset_stream()
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{
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{
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using Regs = HDAudio::Regs;
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using Regs = HDAudio::Regs;
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@@ -219,13 +220,23 @@ namespace Kernel
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// stop stream
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// stop stream
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bar.write8(base + Regs::SDCTL, bar.read8(base + Regs::SDCTL) & 0xFD);
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bar.write8(base + Regs::SDCTL, bar.read8(base + Regs::SDCTL) & 0xFD);
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const auto timeout_ms = SystemTimer::get().ms_since_boot() + 100;
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// reset stream
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// reset stream
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bar.write8(base + Regs::SDCTL, (bar.read8(base + Regs::SDCTL) & 0xFE) | 1);
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bar.write8(base + Regs::SDCTL, (bar.read8(base + Regs::SDCTL) & 0xFE) | 1);
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while (!(bar.read8(base + Regs::SDCTL) & 1))
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while (!(bar.read8(base + Regs::SDCTL) & 1))
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{
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if (SystemTimer::get().ms_since_boot() > timeout_ms)
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return BAN::Error::from_errno(ETIMEDOUT);
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Processor::pause();
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Processor::pause();
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}
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bar.write8(base + Regs::SDCTL, (bar.read8(base + Regs::SDCTL) & 0xFE));
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bar.write8(base + Regs::SDCTL, (bar.read8(base + Regs::SDCTL) & 0xFE));
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while ((bar.read8(base + Regs::SDCTL) & 1))
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while ((bar.read8(base + Regs::SDCTL) & 1))
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{
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if (SystemTimer::get().ms_since_boot() > timeout_ms)
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return BAN::Error::from_errno(ETIMEDOUT);
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Processor::pause();
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Processor::pause();
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}
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// set bdl address, total size and lvi
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// set bdl address, total size and lvi
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const paddr_t bdl_paddr = m_bdl_region->paddr() + bdl_offset();
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const paddr_t bdl_paddr = m_bdl_region->paddr() + bdl_offset();
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@@ -621,7 +632,13 @@ namespace Kernel
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m_bdl_tail = (m_bdl_tail + 1) % m_bdl_entry_count;
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m_bdl_tail = (m_bdl_tail + 1) % m_bdl_entry_count;
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if (m_bdl_tail == m_bdl_head)
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if (m_bdl_tail == m_bdl_head)
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reset_stream();
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{
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if (auto ret = reset_stream(); ret.is_error())
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{
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dwarnln("failed to reset HDA stream: {}", ret.error());
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return;
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}
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}
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queue_bdl_data();
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queue_bdl_data();
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}
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}
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