Kernel: All processors use LAPIC timer when running with APIC

This makes scheduler preemption much cleaner as bsb does not have to
send smp messages to notify other processes about timer interrupt.

Also PIT percision is now "full" 0.8 us instead of 1 ms that I was using
before.

kernel/arch/i686/interrupts.S

@@ -113,6 +113,23 @@ asm_ipi_handler:
 	pop_userspace
 	iret
 
+
+.global asm_timer_handler
+asm_timer_handler:
+	push_userspace
+	load_kernel_segments
+
+	movl %esp, %ebp
+	subl $15, %esp
+	andl $0xFFFFFFF0, %esp
+
+	call cpp_timer_handler
+
+	movl %ebp, %esp
+
+	pop_userspace
+	iret
+
 .macro isr n
 	.global isr\n
 	isr\n:

kernel/arch/x86_64/interrupts.S

@@ -77,6 +77,13 @@ asm_ipi_handler:
 	popaq
 	iretq
 
+.global asm_timer_handler
+asm_timer_handler:
+	pushaq
+	call cpp_timer_handler
+	popaq
+	iretq
+
 .macro isr n
 	.global isr\n
 	isr\n: