Kernel: Unify IDT and GDT code between x86_64 and x86_32
The code is pretty much the same, so there are just couple macros differiating initialization.
This commit is contained in:
@@ -1,21 +0,0 @@
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#include <kernel/GDT.h>
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namespace Kernel
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{
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GDT* GDT::create()
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{
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ASSERT_NOT_REACHED();
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}
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void GDT::write_entry(uint8_t, uint32_t, uint32_t, uint8_t, uint8_t)
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{
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ASSERT_NOT_REACHED();
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}
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void GDT::write_tss()
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{
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ASSERT_NOT_REACHED();
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}
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}
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@@ -1,31 +0,0 @@
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#include <kernel/IDT.h>
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namespace Kernel
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{
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IDT* IDT::create()
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{
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ASSERT_NOT_REACHED();
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}
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[[noreturn]] void IDT::force_triple_fault()
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{
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ASSERT_NOT_REACHED();
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}
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void IDT::register_irq_handler(uint8_t, Interruptable*)
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{
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ASSERT_NOT_REACHED();
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}
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void IDT::register_interrupt_handler(uint8_t, void (*)())
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{
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ASSERT_NOT_REACHED();
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}
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void IDT::register_syscall_handler(uint8_t, void (*)())
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{
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ASSERT_NOT_REACHED();
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}
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}
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134
kernel/arch/i686/interrupts.S
Normal file
134
kernel/arch/i686/interrupts.S
Normal file
@@ -0,0 +1,134 @@
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isr_stub:
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ud2
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pusha
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call cpp_isr_handler
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popa
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iret
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irq_stub:
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ud2
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pusha
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call cpp_irq_handler
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popa
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iret
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// arguments in EAX, EBX, ECX, EDX, ESI, EDI
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.global syscall_asm
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syscall_asm:
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ud2
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pusha
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pushl %esp
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addl $36, (%esp)
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pushl %edi
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pushl %esi
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pushl %edx
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pushl %ecx
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pushl %ebx
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pushl %eax
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call cpp_syscall_handler
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addl $60, %esp
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popl %edi
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popl %esi
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popl %ebp
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addl $4, %esp
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popl %ebx
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popl %edx
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popl %ecx
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addl $4, %esp
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iret
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.macro isr n
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.global isr\n
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isr\n:
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pushl $0
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pushl $\n
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jmp isr_stub
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.endm
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.macro isr_err n
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.global isr\n
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isr\n:
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pushl $\n
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jmp isr_stub
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.endm
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.macro irq n
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.global irq\n
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irq\n:
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pushl $0
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pushl $\n
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jmp irq_stub
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.endm
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isr 0
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isr 1
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isr 2
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isr 3
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isr 4
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isr 5
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isr 6
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isr 7
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isr_err 8
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isr 9
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isr_err 10
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isr_err 11
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isr_err 12
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isr_err 13
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isr_err 14
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isr 15
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isr 16
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isr_err 17
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isr 18
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isr 19
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isr 20
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isr 21
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isr 22
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isr 23
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isr 24
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isr 25
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isr 26
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isr 27
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isr 28
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isr 29
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isr 30
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isr 31
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irq 0
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irq 1
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irq 2
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irq 3
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irq 4
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irq 5
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irq 6
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irq 7
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irq 8
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irq 9
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irq 10
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irq 11
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irq 12
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irq 13
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irq 14
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irq 15
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irq 16
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irq 17
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irq 18
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irq 19
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irq 20
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irq 21
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irq 22
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irq 23
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irq 24
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irq 25
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irq 26
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irq 27
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irq 28
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irq 29
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irq 30
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irq 31
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irq 32
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@@ -1,56 +0,0 @@
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#include <kernel/GDT.h>
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#include <kernel/Debug.h>
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#include <string.h>
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namespace Kernel
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{
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GDT* GDT::create()
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{
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auto* gdt = new GDT();
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ASSERT(gdt);
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gdt->write_entry(0x00, 0x00000000, 0x00000, 0x00, 0x0); // null
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gdt->write_entry(0x08, 0x00000000, 0xFFFFF, 0x9A, 0xA); // kernel code
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gdt->write_entry(0x10, 0x00000000, 0xFFFFF, 0x92, 0xC); // kernel data
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gdt->write_entry(0x18, 0x00000000, 0xFFFFF, 0xFA, 0xA); // user code
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gdt->write_entry(0x20, 0x00000000, 0xFFFFF, 0xF2, 0xC); // user data
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gdt->write_tss();
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return gdt;
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}
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void GDT::write_entry(uint8_t offset, uint32_t base, uint32_t limit, uint8_t access, uint8_t flags)
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{
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ASSERT(offset % sizeof(SegmentDescriptor) == 0);
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uint8_t idx = offset / sizeof(SegmentDescriptor);
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auto& desc = m_gdt[idx];
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desc.base1 = (base >> 0) & 0xFFFF;
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desc.base2 = (base >> 16) & 0xFF;
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desc.base3 = (base >> 24) & 0xFF;
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desc.limit1 = (limit >> 0) & 0xFFFF;
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desc.limit2 = (limit >> 16) & 0x0F;
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desc.access = access & 0xFF;
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desc.flags = flags & 0x0F;
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}
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void GDT::write_tss()
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{
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memset(&m_tss, 0x00, sizeof(TaskStateSegment));
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m_tss.iopb = sizeof(TaskStateSegment);
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uint64_t base = reinterpret_cast<uint64_t>(&m_tss);
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write_entry(0x28, (uint32_t)base, sizeof(TaskStateSegment), 0x89, 0x0);
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auto& desc = m_gdt[0x30 / sizeof(SegmentDescriptor)];
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desc.low = base >> 32;
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desc.high = 0;
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}
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}
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@@ -1,398 +0,0 @@
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#include <BAN/Array.h>
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#include <BAN/Errors.h>
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#include <kernel/IDT.h>
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#include <kernel/InterruptController.h>
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#include <kernel/InterruptStack.h>
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#include <kernel/Memory/kmalloc.h>
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#include <kernel/Panic.h>
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#include <kernel/Process.h>
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#include <kernel/Scheduler.h>
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#include <kernel/Timer/PIT.h>
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#define ISR_LIST_X X(0) X(1) X(2) X(3) X(4) X(5) X(6) X(7) X(8) X(9) X(10) X(11) X(12) X(13) X(14) X(15) X(16) X(17) X(18) X(19) X(20) X(21) X(22) X(23) X(24) X(25) X(26) X(27) X(28) X(29) X(30) X(31)
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#define IRQ_LIST_X X(0) X(1) X(2) X(3) X(4) X(5) X(6) X(7) X(8) X(9) X(10) X(11) X(12) X(13) X(14) X(15) X(16) X(17) X(18) X(19) X(20) X(21) X(22) X(23) X(24) X(25) X(26) X(27) X(28) X(29) X(30) X(31) X(32)
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namespace Kernel
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{
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struct Registers
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{
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uint64_t rsp;
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uint64_t rip;
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uint64_t rflags;
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uint64_t cr4;
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uint64_t cr3;
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uint64_t cr2;
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uint64_t cr0;
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uint64_t r15;
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uint64_t r14;
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uint64_t r13;
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uint64_t r12;
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uint64_t r11;
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uint64_t r10;
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uint64_t r9;
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uint64_t r8;
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uint64_t rsi;
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uint64_t rdi;
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uint64_t rbp;
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uint64_t rdx;
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uint64_t rcx;
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uint64_t rbx;
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uint64_t rax;
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};
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#define X(num) 1 +
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static BAN::Array<Interruptable*, IRQ_LIST_X 0> s_interruptables;
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#undef X
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enum ISR
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{
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DivisionError,
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Debug,
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NonMaskableInterrupt,
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Breakpoint,
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Overflow,
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BoundRangeException,
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InvalidOpcode,
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DeviceNotAvailable,
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DoubleFault,
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CoprocessorSegmentOverrun,
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InvalidTSS,
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SegmentNotPresent,
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StackSegmentFault,
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GeneralProtectionFault,
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PageFault,
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UnknownException0x0F,
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x87FloatingPointException,
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AlignmentCheck,
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MachineCheck,
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SIMDFloatingPointException,
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VirtualizationException,
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ControlProtectionException,
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UnknownException0x16,
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UnknownException0x17,
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UnknownException0x18,
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UnknownException0x19,
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UnknownException0x1A,
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UnknownException0x1B,
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HypervisorInjectionException,
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VMMCommunicationException,
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SecurityException,
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UnkownException0x1F,
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};
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struct PageFaultError
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{
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union
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{
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uint32_t raw;
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struct
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{
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uint32_t present : 1;
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uint32_t write : 1;
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uint32_t userspace : 1;
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uint32_t reserved_write : 1;
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uint32_t instruction : 1;
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uint32_t protection_key : 1;
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uint32_t shadow_stack : 1;
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uint32_t reserved1 : 8;
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uint32_t sgx_violation : 1;
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uint32_t reserved2 : 16;
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};
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};
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};
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static_assert(sizeof(PageFaultError) == 4);
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static const char* isr_exceptions[] =
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{
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"Division Error",
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"Debug",
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"Non-maskable Interrupt",
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"Breakpoint",
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"Overflow",
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"Bound Range Exception",
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"Invalid Opcode",
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"Device Not Available",
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"Double Fault",
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"Coprocessor Segment Overrun",
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"Invalid TSS",
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"Segment Not Present",
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"Stack-Segment Fault",
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"General Protection Fault",
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"Page Fault",
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"Unknown Exception 0x0F",
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"x87 Floating-Point Exception",
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"Alignment Check",
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"Machine Check",
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"SIMD Floating-Point Exception",
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"Virtualization Exception",
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"Control Protection Exception",
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"Unknown Exception 0x16",
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"Unknown Exception 0x17",
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"Unknown Exception 0x18",
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"Unknown Exception 0x19",
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"Unknown Exception 0x1A",
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"Unknown Exception 0x1B",
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"Hypervisor Injection Exception",
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"VMM Communication Exception",
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"Security Exception",
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"Unkown Exception 0x1F",
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};
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extern "C" void cpp_isr_handler(uint64_t isr, uint64_t error, InterruptStack& interrupt_stack, const Registers* regs)
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{
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if (g_paniced)
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{
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dprintln("Processor {} halted", Processor::current_id());
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InterruptController::get().broadcast_ipi();
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asm volatile("cli; 1: hlt; jmp 1b");
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}
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#if __enable_sse
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bool from_userspace = (interrupt_stack.cs & 0b11) == 0b11;
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if (from_userspace)
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Thread::current().save_sse();
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#endif
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pid_t tid = Scheduler::current_tid();
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pid_t pid = tid ? Process::current().pid() : 0;
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if (tid)
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{
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Thread::current().set_return_sp(interrupt_stack.sp);
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Thread::current().set_return_ip(interrupt_stack.ip);
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if (isr == ISR::PageFault)
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{
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// Check if stack is OOB
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auto& stack = Thread::current().stack();
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auto& istack = Thread::current().interrupt_stack();
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if (stack.vaddr() < interrupt_stack.sp && interrupt_stack.sp <= stack.vaddr() + stack.size())
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; // using normal stack
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else if (istack.vaddr() < interrupt_stack.sp && interrupt_stack.sp <= istack.vaddr() + istack.size())
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; // using interrupt stack
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else
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{
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derrorln("Stack pointer out of bounds!");
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derrorln("rip {H}", interrupt_stack.ip);
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derrorln("rsp {H}, stack {H}->{H}, istack {H}->{H}",
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interrupt_stack.sp,
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stack.vaddr(), stack.vaddr() + stack.size(),
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istack.vaddr(), istack.vaddr() + istack.size()
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);
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Thread::current().handle_signal(SIGKILL);
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goto done;
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}
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// Try demand paging on non present pages
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PageFaultError page_fault_error;
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page_fault_error.raw = error;
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if (!page_fault_error.present)
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{
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asm volatile("sti");
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auto result = Process::current().allocate_page_for_demand_paging(regs->cr2);
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asm volatile("cli");
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if (!result.is_error() && result.value())
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goto done;
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if (result.is_error())
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{
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dwarnln("Demand paging: {}", result.error());
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Thread::current().handle_signal(SIGKILL);
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goto done;
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}
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}
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}
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#if __enable_sse
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else if (isr == ISR::DeviceNotAvailable)
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{
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asm volatile(
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"movq %cr0, %rax;"
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"andq $~(1 << 3), %rax;"
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"movq %rax, %cr0;"
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);
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if (auto* current = &Thread::current(); current != Thread::sse_thread())
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{
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if (auto* sse = Thread::sse_thread())
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sse->save_sse();
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current->load_sse();
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}
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goto done;
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}
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#endif
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}
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if (PageTable::current().get_page_flags(interrupt_stack.ip & PAGE_ADDR_MASK) & PageTable::Flags::Present)
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{
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auto* machine_code = (const uint8_t*)interrupt_stack.ip;
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dwarnln("While executing: {2H}{2H}{2H}{2H}{2H}{2H}{2H}{2H}",
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machine_code[0],
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machine_code[1],
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machine_code[2],
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machine_code[3],
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machine_code[4],
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machine_code[5],
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machine_code[6],
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machine_code[7]
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);
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}
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dwarnln(
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"{} (error code: 0x{16H}), pid {}, tid {}\r\n"
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"Register dump\r\n"
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"rax=0x{16H}, rbx=0x{16H}, rcx=0x{16H}, rdx=0x{16H}\r\n"
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"rsp=0x{16H}, rbp=0x{16H}, rdi=0x{16H}, rsi=0x{16H}\r\n"
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"rip=0x{16H}, rflags=0x{16H}\r\n"
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"cr0=0x{16H}, cr2=0x{16H}, cr3=0x{16H}, cr4=0x{16H}",
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isr_exceptions[isr], error, pid, tid,
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regs->rax, regs->rbx, regs->rcx, regs->rdx,
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regs->rsp, regs->rbp, regs->rdi, regs->rsi,
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regs->rip, regs->rflags,
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regs->cr0, regs->cr2, regs->cr3, regs->cr4
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);
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if (isr == ISR::PageFault)
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PageTable::current().debug_dump();
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Debug::dump_stack_trace();
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if (tid && Thread::current().is_userspace())
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{
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// TODO: Confirm and fix the exception to signal mappings
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int signal = 0;
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switch (isr)
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{
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case ISR::DivisionError:
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case ISR::SIMDFloatingPointException:
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case ISR::x87FloatingPointException:
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signal = SIGFPE;
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break;
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case ISR::AlignmentCheck:
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signal = SIGBUS;
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break;
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||||
case ISR::InvalidOpcode:
|
||||
signal = SIGILL;
|
||||
break;
|
||||
case ISR::PageFault:
|
||||
signal = SIGSEGV;
|
||||
break;
|
||||
default:
|
||||
dwarnln("Unhandled exception");
|
||||
signal = SIGABRT;
|
||||
break;
|
||||
}
|
||||
|
||||
Thread::current().handle_signal(signal);
|
||||
}
|
||||
else
|
||||
{
|
||||
panic("Unhandled exception");
|
||||
}
|
||||
|
||||
ASSERT(Thread::current().state() != Thread::State::Terminated);
|
||||
|
||||
done:
|
||||
return;
|
||||
}
|
||||
|
||||
extern "C" void cpp_irq_handler(uint64_t irq, InterruptStack& interrupt_stack)
|
||||
{
|
||||
if (g_paniced)
|
||||
{
|
||||
dprintln("Processor {} halted", Processor::current_id());
|
||||
InterruptController::get().broadcast_ipi();
|
||||
asm volatile("cli; 1: hlt; jmp 1b");
|
||||
}
|
||||
|
||||
if (Scheduler::current_tid())
|
||||
{
|
||||
Thread::current().set_return_sp(interrupt_stack.sp);
|
||||
Thread::current().set_return_ip(interrupt_stack.ip);
|
||||
}
|
||||
|
||||
if (!InterruptController::get().is_in_service(irq))
|
||||
dprintln("spurious irq 0x{2H}", irq);
|
||||
else
|
||||
{
|
||||
InterruptController::get().eoi(irq);
|
||||
if (irq == IRQ_IPI)
|
||||
Scheduler::get().reschedule();
|
||||
else if (auto* handler = s_interruptables[irq])
|
||||
handler->handle_irq();
|
||||
else
|
||||
dprintln("no handler for irq 0x{2H}", irq);
|
||||
}
|
||||
|
||||
Scheduler::get().reschedule_if_idling();
|
||||
|
||||
ASSERT(Thread::current().state() != Thread::State::Terminated);
|
||||
}
|
||||
|
||||
void IDT::register_interrupt_handler(uint8_t index, void (*handler)())
|
||||
{
|
||||
auto& descriptor = m_idt[index];
|
||||
descriptor.offset1 = (uint16_t)((uint64_t)handler >> 0);
|
||||
descriptor.offset2 = (uint16_t)((uint64_t)handler >> 16);
|
||||
descriptor.offset3 = (uint32_t)((uint64_t)handler >> 32);
|
||||
|
||||
descriptor.selector = 0x08;
|
||||
descriptor.IST = 0;
|
||||
descriptor.flags = 0x8E;
|
||||
}
|
||||
|
||||
void IDT::register_syscall_handler(uint8_t index, void (*handler)())
|
||||
{
|
||||
register_interrupt_handler(index, handler);
|
||||
m_idt[index].flags = 0xEE;
|
||||
}
|
||||
|
||||
void IDT::register_irq_handler(uint8_t irq, Interruptable* interruptable)
|
||||
{
|
||||
if (irq > s_interruptables.size())
|
||||
Kernel::panic("Trying to assign handler for irq {} while only {} are supported", irq, s_interruptables.size());
|
||||
s_interruptables[irq] = interruptable;
|
||||
}
|
||||
|
||||
#define X(num) extern "C" void isr ## num();
|
||||
ISR_LIST_X
|
||||
#undef X
|
||||
|
||||
#define X(num) extern "C" void irq ## num();
|
||||
IRQ_LIST_X
|
||||
#undef X
|
||||
|
||||
extern "C" void syscall_asm();
|
||||
|
||||
IDT* IDT::create()
|
||||
{
|
||||
auto* idt = new IDT();
|
||||
ASSERT(idt);
|
||||
|
||||
memset(idt->m_idt.data(), 0x00, 0x100 * sizeof(GateDescriptor));
|
||||
|
||||
#define X(num) idt->register_interrupt_handler(num, isr ## num);
|
||||
ISR_LIST_X
|
||||
#undef X
|
||||
|
||||
#define X(num) idt->register_interrupt_handler(IRQ_VECTOR_BASE + num, irq ## num);
|
||||
IRQ_LIST_X
|
||||
#undef X
|
||||
|
||||
idt->register_syscall_handler(0x80, syscall_asm);
|
||||
|
||||
return idt;
|
||||
}
|
||||
|
||||
[[noreturn]] void IDT::force_triple_fault()
|
||||
{
|
||||
// load 0 sized IDT and trigger an interrupt to force triple fault
|
||||
Processor::set_interrupt_state(InterruptState::Disabled);
|
||||
Processor::idt().m_idtr.size = 0;
|
||||
Processor::idt().load();
|
||||
asm volatile("int $0x00");
|
||||
ASSERT_NOT_REACHED();
|
||||
}
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user