1000th COMMIT: Kernel: Add basic E1000 driver
This driver is only capable to read mac address and enable and read link status
This commit is contained in:
Bananymous
parent
5fae3cec2a
commit
14a608effd
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@ -38,6 +38,7 @@ set(KERNEL_SOURCES
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kernel/Memory/kmalloc.cpp
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kernel/Memory/PhysicalRange.cpp
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kernel/Memory/VirtualRange.cpp
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kernel/Networking/E1000.cpp
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kernel/OpenFileDescriptorSet.cpp
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kernel/Panic.cpp
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kernel/PCI.cpp
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@ -0,0 +1,58 @@
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#pragma once
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#include <BAN/UniqPtr.h>
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#include <kernel/Networking/NetworkDriver.h>
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#include <kernel/PCI.h>
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#define E1000_NUM_RX_DESC 32
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#define E1000_NUM_TX_DESC 8
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namespace Kernel
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{
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class E1000 final : public NetworkDriver
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{
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public:
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static BAN::ErrorOr<BAN::UniqPtr<E1000>> create(const PCIDevice&);
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~E1000();
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virtual uint8_t* get_mac_address() override { return m_mac_address; }
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virtual BAN::ErrorOr<void> send_packet(const void* data, uint16_t len) override;
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virtual bool link_up() override { return m_link_up; }
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virtual int link_speed() override;
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private:
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E1000() = default;
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BAN::ErrorOr<void> initialize(const PCIDevice&);
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static void interrupt_handler();
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void write32(uint16_t reg, uint32_t value);
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uint32_t read32(uint16_t reg);
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void detect_eeprom();
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uint32_t eeprom_read(uint8_t addr);
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BAN::ErrorOr<void> read_mac_address();
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void initialize_rx();
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void initialize_tx();
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void enable_link();
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void enable_interrupts();
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void handle_receive();
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private:
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PCIDevice::BarType m_bar_type {};
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uint64_t m_bar_addr {};
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bool m_has_eerprom { false };
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uint8_t m_mac_address[6] {};
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uint16_t m_rx_current {};
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uint16_t m_tx_current {};
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struct e1000_rx_desc* m_rx_descs[E1000_NUM_RX_DESC] {};
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struct e1000_tx_desc* m_tx_descs[E1000_NUM_TX_DESC] {};
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bool m_link_up { false };
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};
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}
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@ -0,0 +1,20 @@
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#pragma once
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#include <BAN/Errors.h>
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namespace Kernel
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{
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class NetworkDriver
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{
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public:
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virtual ~NetworkDriver() {}
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virtual uint8_t* get_mac_address() = 0;
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virtual BAN::ErrorOr<void> send_packet(const void* data, uint16_t len) = 0;
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virtual bool link_up() = 0;
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virtual int link_speed() = 0;
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};
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}
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@ -7,6 +7,14 @@ namespace Kernel
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class PCIDevice
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{
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public:
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enum class BarType
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{
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INVAL,
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MEM,
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IO,
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};
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public:
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PCIDevice(uint8_t, uint8_t, uint8_t);
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@ -24,6 +32,9 @@ namespace Kernel
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uint8_t subclass() const { return m_subclass; }
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uint8_t prog_if() const { return m_prog_if; }
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BarType read_bar_type(uint8_t) const;
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uint64_t read_bar_address(uint8_t) const;
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void enable_bus_mastering() const;
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void disable_bus_mastering() const;
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@ -41,6 +52,8 @@ namespace Kernel
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uint8_t m_class_code;
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uint8_t m_subclass;
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uint8_t m_prog_if;
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uint8_t m_header_type;
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};
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class PCI
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@ -0,0 +1,381 @@
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#include <kernel/IDT.h>
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#include <kernel/InterruptController.h>
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#include <kernel/IO.h>
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#include <kernel/Memory/PageTable.h>
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#include <kernel/MMIO.h>
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#include <kernel/Networking/E1000.h>
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#define E1000_GENERAL_MEM_SIZE (128 * 1024)
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#define E1000_REG_CTRL 0x0000
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#define E1000_REG_STATUS 0x0008
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#define E1000_REG_EEPROM 0x0014
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#define E1000_REG_INT_CAUSE_READ 0x00C0
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#define E1000_REG_INT_RATE 0x00C4
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#define E1000_REG_INT_MASK_SET 0x00D0
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#define E1000_REG_INT_MASK_CLEAR 0x00D8
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#define E1000_REG_RCTRL 0x0100
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#define E1000_REG_RXDESCLO 0x2800
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#define E1000_REG_RXDESCHI 0x2804
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#define E1000_REG_RXDESCLEN 0x2808
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#define E1000_REG_RXDESCHEAD 0x2810
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#define E1000_REG_RXDESCTAIL 0x2818
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#define E1000_REG_TXDESCLO 0x3800
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#define E1000_REG_TXDESCHI 0x3804
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#define E1000_REG_TXDESCLEN 0x3808
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#define E1000_REG_TXDESCHEAD 0x3810
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#define E1000_REG_TXDESCTAIL 0x3818
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#define E1000_REG_TCTRL 0x0400
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#define E1000_REG_TIPG 0x0410
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#define E1000_STATUS_LINK_UP 0x02
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#define E1000_STATUS_SPEED_MASK 0xC0
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#define E1000_STATUS_SPEED_10MB 0x00
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#define E1000_STATUS_SPEED_100MB 0x40
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#define E1000_STATUS_SPEED_1000MB1 0x80
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#define E1000_STATUS_SPEED_1000MB2 0xC0
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#define E1000_CTRL_SET_LINK_UP 0x40
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#define E1000_INT_TXDW (1 << 0)
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#define E1000_INT_TXQE (1 << 1)
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#define E1000_INT_LSC (1 << 2)
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#define E1000_INT_RXSEQ (1 << 3)
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#define E1000_INT_RXDMT0 (1 << 4)
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#define E1000_INT_RXO (1 << 6)
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#define E1000_INT_RXT0 (1 << 7)
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#define E1000_INT_MDAC (1 << 9)
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#define E1000_INT_RXCFG (1 << 10)
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#define E1000_INT_PHYINT (1 << 12)
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#define E1000_INT_TXD_LOW (1 << 15)
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#define E1000_INT_SRPD (1 << 16)
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#define E1000_TCTL_EN (1 << 1)
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#define E1000_TCTL_PSP (1 << 3)
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#define E1000_TCTL_CT_SHIFT 4
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#define E1000_TCTL_COLD_SHIFT 12
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#define E1000_TCTL_SWXOFF (1 << 22)
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#define E1000_TCTL_RTLC (1 << 24)
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#define E1000_RCTL_EN (1 << 1)
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#define E1000_RCTL_SBP (1 << 2)
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#define E1000_RCTL_UPE (1 << 3)
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#define E1000_RCTL_MPE (1 << 4)
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#define E1000_RCTL_LPE (1 << 5)
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#define E1000_RCTL_LBM_NONE (0 << 6)
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#define E1000_RCTL_LBM_PHY (3 << 6)
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#define E1000_RTCL_RDMTS_HALF (0 << 8)
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#define E1000_RTCL_RDMTS_QUARTER (1 << 8)
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#define E1000_RTCL_RDMTS_EIGHTH (2 << 8)
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#define E1000_RCTL_MO_36 (0 << 12)
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#define E1000_RCTL_MO_35 (1 << 12)
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#define E1000_RCTL_MO_34 (2 << 12)
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#define E1000_RCTL_MO_32 (3 << 12)
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#define E1000_RCTL_BAM (1 << 15)
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#define E1000_RCTL_VFE (1 << 18)
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#define E1000_RCTL_CFIEN (1 << 19)
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#define E1000_RCTL_CFI (1 << 20)
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#define E1000_RCTL_DPF (1 << 22)
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#define E1000_RCTL_PMCF (1 << 23)
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#define E1000_RCTL_SECRC (1 << 26)
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#define E1000_RCTL_BSIZE_256 (3 << 16)
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#define E1000_RCTL_BSIZE_512 (2 << 16)
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#define E1000_RCTL_BSIZE_1024 (1 << 16)
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#define E1000_RCTL_BSIZE_2048 (0 << 16)
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#define E1000_RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
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#define E1000_RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
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#define E1000_RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
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namespace Kernel
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{
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struct e1000_rx_desc
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{
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volatile uint64_t addr;
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volatile uint16_t length;
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volatile uint16_t checksum;
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volatile uint8_t status;
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volatile uint8_t errors;
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volatile uint16_t special;
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} __attribute__((packed));
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struct e1000_tx_desc
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{
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volatile uint64_t addr;
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volatile uint16_t length;
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volatile uint8_t cso;
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volatile uint8_t cmd;
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volatile uint8_t status;
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volatile uint8_t css;
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volatile uint16_t special;
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} __attribute__((packed));
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BAN::ErrorOr<BAN::UniqPtr<E1000>> E1000::create(const PCIDevice& pci_device)
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{
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E1000* e1000 = new E1000();
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ASSERT(e1000);
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if (auto ret = e1000->initialize(pci_device); ret.is_error())
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{
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delete e1000;
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return ret.release_error();
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}
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return BAN::UniqPtr<E1000>::adopt(e1000);
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}
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E1000::~E1000()
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{
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if (m_bar_type == PCIDevice::BarType::MEM && m_bar_addr)
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PageTable::kernel().unmap_range(m_bar_addr & PAGE_ADDR_MASK, E1000_GENERAL_MEM_SIZE);
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}
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BAN::ErrorOr<void> E1000::initialize(const PCIDevice& pci_device)
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{
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m_bar_type = pci_device.read_bar_type(0);
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if (m_bar_type == PCIDevice::BarType::INVAL)
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{
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dwarnln("invalid bar0 type");
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return BAN::Error::from_errno(EINVAL);
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}
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if (m_bar_type == PCIDevice::BarType::MEM)
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{
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uint64_t bar_addr = pci_device.read_bar_address(0);
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vaddr_t page_vaddr = PageTable::kernel().reserve_free_contiguous_pages(E1000_GENERAL_MEM_SIZE / PAGE_SIZE, KERNEL_OFFSET);
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paddr_t page_paddr = bar_addr & PAGE_ADDR_MASK;
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PageTable::kernel().map_range_at(page_paddr, page_vaddr, E1000_GENERAL_MEM_SIZE, PageTable::Flags::CacheDisable | PageTable::Flags::ReadWrite | PageTable::Flags::Present);
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m_bar_addr = page_vaddr + (bar_addr % PAGE_SIZE);
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}
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else if (m_bar_type == PCIDevice::BarType::IO)
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{
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m_bar_addr = pci_device.read_bar_address(0);
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}
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pci_device.enable_bus_mastering();
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detect_eeprom();
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TRY(read_mac_address());
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dprintln("E1000 at PCI {}:{}.{}", pci_device.bus(), pci_device.dev(), pci_device.func());
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dprintln(" MAC: {2H}:{2H}:{2H}:{2H}:{2H}:{2H}",
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m_mac_address[0],
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m_mac_address[1],
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m_mac_address[2],
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m_mac_address[3],
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m_mac_address[4],
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m_mac_address[5]
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);
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initialize_rx();
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initialize_tx();
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enable_link();
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enable_interrupts();
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dprintln(" link up: {}", link_up());
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if (link_up())
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dprintln(" link speed: {} Mbps", link_speed());
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return {};
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}
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void E1000::write32(uint16_t reg, uint32_t value)
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{
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switch (m_bar_type)
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{
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case PCIDevice::BarType::MEM:
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MMIO::write32(m_bar_addr + reg, value);
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break;
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case PCIDevice::BarType::IO:
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IO::outl(m_bar_addr, reg);
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IO::outl(m_bar_addr + 4, value);
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break;
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default:
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ASSERT_NOT_REACHED();
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}
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}
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uint32_t E1000::read32(uint16_t reg)
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{
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uint32_t result = 0;
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switch (m_bar_type)
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{
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case PCIDevice::BarType::MEM:
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result = MMIO::read32(m_bar_addr + reg);
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break;
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case PCIDevice::BarType::IO:
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IO::outl(m_bar_addr, reg);
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result = IO::inl(m_bar_addr + 4);
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break;
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default:
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ASSERT_NOT_REACHED();
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}
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return result;
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}
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void E1000::detect_eeprom()
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{
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m_has_eerprom = false;
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write32(E1000_REG_EEPROM, 0x01);
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for (int i = 0; i < 1000 && !m_has_eerprom; i++)
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if (read32(E1000_REG_EEPROM) & 0x10)
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m_has_eerprom = true;
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}
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uint32_t E1000::eeprom_read(uint8_t address)
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{
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uint32_t tmp = 0;
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if (m_has_eerprom)
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{
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write32(E1000_REG_EEPROM, ((uint32_t)address << 8) | 1);
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while (!((tmp = read32(E1000_REG_EEPROM)) & (1 << 4)))
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continue;
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}
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else
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{
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write32(E1000_REG_EEPROM, ((uint32_t)address << 2) | 1);
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while (!((tmp = read32(E1000_REG_EEPROM)) & (1 << 1)))
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continue;
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}
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return (tmp >> 16) & 0xFFFF;
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}
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BAN::ErrorOr<void> E1000::read_mac_address()
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{
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if (m_has_eerprom)
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{
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uint32_t temp = eeprom_read(0);
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m_mac_address[0] = temp;
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m_mac_address[1] = temp >> 8;
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temp = eeprom_read(1);
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m_mac_address[2] = temp;
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m_mac_address[3] = temp >> 8;
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temp = eeprom_read(2);
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m_mac_address[4] = temp;
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m_mac_address[5] = temp >> 8;
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return {};
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}
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if (read32(0x5400) == 0)
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{
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dwarnln("no mac address");
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return BAN::Error::from_errno(EINVAL);
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}
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for (int i = 0; i < 6; i++)
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m_mac_address[i] = (uint8_t)read32(0x5400 + i * 8);
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return {};
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}
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void E1000::initialize_rx()
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{
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uint8_t* ptr = (uint8_t*)kmalloc(sizeof(e1000_rx_desc) * E1000_NUM_RX_DESC + 16, 16, true);
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ASSERT(ptr);
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e1000_rx_desc* descs = (e1000_rx_desc*)ptr;
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for (int i = 0; i < E1000_NUM_RX_DESC; i++)
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{
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// FIXME
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m_rx_descs[i] = &descs[i];
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m_rx_descs[i]->addr = 0;
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m_rx_descs[i]->status = 0;
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}
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write32(E1000_REG_RXDESCLO, (uintptr_t)ptr >> 32);
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write32(E1000_REG_RXDESCHI, (uintptr_t)ptr & 0xFFFFFFFF);
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write32(E1000_REG_RXDESCLEN, E1000_NUM_RX_DESC * sizeof(e1000_rx_desc));
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write32(E1000_REG_RXDESCHEAD, 0);
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write32(E1000_REG_RXDESCTAIL, E1000_NUM_RX_DESC - 1);
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m_rx_current = 0;
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uint32_t rctrl = 0;
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rctrl |= E1000_RCTL_EN;
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rctrl |= E1000_RCTL_SBP;
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rctrl |= E1000_RCTL_UPE;
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rctrl |= E1000_RCTL_MPE;
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rctrl |= E1000_RCTL_LBM_NONE;
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rctrl |= E1000_RTCL_RDMTS_HALF;
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rctrl |= E1000_RCTL_BAM;
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rctrl |= E1000_RCTL_SECRC;
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rctrl |= E1000_RCTL_BSIZE_8192;
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write32(E1000_REG_RCTRL, rctrl);
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}
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void E1000::initialize_tx()
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{
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auto* ptr = (uint8_t*)kmalloc(sizeof(e1000_tx_desc) * E1000_NUM_TX_DESC + 16, 16, true);
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ASSERT(ptr);
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auto* descs = (e1000_tx_desc*)ptr;
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for(int i = 0; i < E1000_NUM_TX_DESC; i++)
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{
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// FIXME
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m_tx_descs[i] = &descs[i];
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m_tx_descs[i]->addr = 0;
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m_tx_descs[i]->cmd = 0;
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}
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write32(E1000_REG_TXDESCHI, (uintptr_t)ptr >> 32);
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write32(E1000_REG_TXDESCLO, (uintptr_t)ptr & 0xFFFFFFFF);
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write32(E1000_REG_TXDESCLEN, E1000_NUM_TX_DESC * sizeof(e1000_tx_desc));
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write32(E1000_REG_TXDESCHEAD, 0);
|
||||
write32(E1000_REG_TXDESCTAIL, 0);
|
||||
|
||||
m_tx_current = 0;
|
||||
|
||||
write32(E1000_REG_TCTRL, read32(E1000_REG_TCTRL) | E1000_TCTL_EN | E1000_TCTL_PSP);
|
||||
write32(E1000_REG_TIPG, 0x0060200A);
|
||||
}
|
||||
|
||||
void E1000::enable_link()
|
||||
{
|
||||
write32(E1000_REG_CTRL, read32(E1000_REG_CTRL) | E1000_CTRL_SET_LINK_UP);
|
||||
m_link_up = !!(read32(E1000_REG_STATUS) & E1000_STATUS_LINK_UP);
|
||||
}
|
||||
|
||||
int E1000::link_speed()
|
||||
{
|
||||
if (!link_up())
|
||||
return 0;
|
||||
uint32_t speed = read32(E1000_REG_STATUS) & E1000_STATUS_SPEED_MASK;
|
||||
if (speed == E1000_STATUS_SPEED_10MB)
|
||||
return 10;
|
||||
if (speed == E1000_STATUS_SPEED_100MB)
|
||||
return 100;
|
||||
if (speed == E1000_STATUS_SPEED_1000MB1)
|
||||
return 1000;
|
||||
if (speed == E1000_STATUS_SPEED_1000MB2)
|
||||
return 1000;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void E1000::enable_interrupts()
|
||||
{
|
||||
write32(E1000_REG_INT_RATE, 6000);
|
||||
write32(E1000_REG_INT_MASK_SET, E1000_INT_LSC | E1000_INT_RXT0 | E1000_INT_RXO);
|
||||
read32(E1000_REG_INT_CAUSE_READ);
|
||||
|
||||
// FIXME: implement PCI interrupt allocation
|
||||
//IDT::register_irq_handler(irq, E1000::interrupt_handler);
|
||||
//InterruptController::enable_irq(irq);
|
||||
}
|
||||
|
||||
BAN::ErrorOr<void> E1000::send_packet(const void* data, uint16_t len)
|
||||
{
|
||||
(void)data;
|
||||
(void)len;
|
||||
return BAN::Error::from_errno(ENOTSUP);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#include <kernel/IO.h>
|
||||
#include <kernel/Networking/E1000.h>
|
||||
#include <kernel/PCI.h>
|
||||
#include <kernel/Storage/ATAController.h>
|
||||
|
||||
|
|
@ -105,7 +106,7 @@ namespace Kernel
|
|||
{
|
||||
case 0x01:
|
||||
if (auto res = ATAController::create(pci_device); res.is_error())
|
||||
dprintln("{}", res.error());
|
||||
dprintln("ATA: {}", res.error());
|
||||
break;
|
||||
default:
|
||||
dprintln("unsupported storage device (pci {2H}.{2H}.{2H})", pci_device.class_code(), pci_device.subclass(), pci_device.prog_if());
|
||||
|
|
@ -113,6 +114,20 @@ namespace Kernel
|
|||
}
|
||||
break;
|
||||
}
|
||||
case 0x02:
|
||||
{
|
||||
switch (pci_device.subclass())
|
||||
{
|
||||
case 0x00:
|
||||
if (auto res = E1000::create(pci_device); res.is_error())
|
||||
dprintln("E1000: {}", res.error());
|
||||
break;
|
||||
default:
|
||||
dprintln("unsupported ethernet device (pci {2H}.{2H}.{2H})", pci_device.class_code(), pci_device.subclass(), pci_device.prog_if());
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -126,6 +141,7 @@ namespace Kernel
|
|||
m_class_code = (uint8_t)(type >> 8);
|
||||
m_subclass = (uint8_t)(type);
|
||||
m_prog_if = read_byte(0x09);
|
||||
m_header_type = read_byte(0x0E);
|
||||
}
|
||||
|
||||
uint32_t PCIDevice::read_dword(uint8_t offset) const
|
||||
|
|
@ -153,6 +169,33 @@ namespace Kernel
|
|||
write_config_dword(m_bus, m_dev, m_func, offset, value);
|
||||
}
|
||||
|
||||
PCIDevice::BarType PCIDevice::read_bar_type(uint8_t bar) const
|
||||
{
|
||||
ASSERT(m_header_type == 0x00);
|
||||
ASSERT(bar <= 5);
|
||||
|
||||
uint32_t type = read_dword(0x10 + bar * 4) & 0b111;
|
||||
if (type & 1)
|
||||
return BarType::IO;
|
||||
type >>= 1;
|
||||
if (type == 0x0 || type == 0x2)
|
||||
return BarType::MEM;
|
||||
return BarType::INVAL;
|
||||
}
|
||||
|
||||
uint64_t PCIDevice::read_bar_address(uint8_t bar) const
|
||||
{
|
||||
ASSERT(m_header_type == 0x00);
|
||||
ASSERT(bar <= 5);
|
||||
|
||||
uint64_t address = read_dword(0x10 + bar * 4);
|
||||
if (address & 1)
|
||||
return address & 0xFFFFFFFC;
|
||||
if ((address & 0b110) == 0b100)
|
||||
address |= (uint64_t)read_dword(0x10 + bar * 4 + 4) << 32;
|
||||
return address & 0xFFFFFFFFFFFFFFF0;
|
||||
}
|
||||
|
||||
void PCIDevice::enable_bus_mastering() const
|
||||
{
|
||||
write_dword(0x04, read_dword(0x04) | 1u << 2);
|
||||
|
|
|
|||
Loading…
Reference in New Issue