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Kernel: PCI devices can now create region for BAR

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This creates either MEM or IO region for read/write access to PCI
device.
This commit is contained in:
Bananymous
2023-09-18 13:53:10 +03:00
parent a740bf8df4
commit 11717f90c1
7 changed files with 296 additions and 155 deletions
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262
kernel/kernel/PCI.cpp
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@@ -1,33 +1,22 @@
#include <kernel/IO.h>
#include <kernel/Memory/PageTable.h>
#include <kernel/MMIO.h>
#include <kernel/Networking/E1000.h>
#include <kernel/PCI.h>
#include <kernel/Storage/ATAController.h>
#define INVALID 0xFFFF
#define INVALID_VENDOR 0xFFFF
#define MULTI_FUNCTION 0x80
#define CONFIG_ADDRESS 0xCF8
#define CONFIG_DATA 0xCFC
namespace Kernel
#define DEBUG_PCI 1
namespace Kernel::PCI
{
static PCI* s_instance = nullptr;
void PCI::initialize()
{
ASSERT(s_instance == nullptr);
s_instance = new PCI();
ASSERT(s_instance);
s_instance->check_all_buses();
s_instance->initialize_devices();
}
PCI& PCI::get()
{
ASSERT(s_instance);
return *s_instance;
}
static PCIManager* s_instance = nullptr;
static uint32_t read_config_dword(uint8_t bus, uint8_t dev, uint8_t func, uint8_t offset)
{
@@ -55,7 +44,22 @@ namespace Kernel
return (dword >> 16) & 0xFF;
}
void PCI::check_function(uint8_t bus, uint8_t dev, uint8_t func)
void PCIManager::initialize()
{
ASSERT(s_instance == nullptr);
s_instance = new PCIManager();
ASSERT(s_instance);
s_instance->check_all_buses();
s_instance->initialize_devices();
}
PCIManager& PCIManager::get()
{
ASSERT(s_instance);
return *s_instance;
}
void PCIManager::check_function(uint8_t bus, uint8_t dev, uint8_t func)
{
MUST(m_devices.emplace_back(bus, dev, func));
auto& device = m_devices.back();
@@ -63,29 +67,29 @@ namespace Kernel
check_bus(device.read_byte(0x19));
}
void PCI::check_device(uint8_t bus, uint8_t dev)
void PCIManager::check_device(uint8_t bus, uint8_t dev)
{
if (get_vendor_id(bus, dev, 0) == INVALID)
if (get_vendor_id(bus, dev, 0) == INVALID_VENDOR)
return;
check_function(bus, dev, 0);
if (get_header_type(bus, dev, 0) & MULTI_FUNCTION)
for (uint8_t func = 1; func < 8; func++)
if (get_vendor_id(bus, dev, func) != INVALID)
if (get_vendor_id(bus, dev, func) != INVALID_VENDOR)
check_function(bus, dev, func);
}
void PCI::check_bus(uint8_t bus)
void PCIManager::check_bus(uint8_t bus)
{
for (uint8_t dev = 0; dev < 32; dev++)
check_device(bus, dev);
}
void PCI::check_all_buses()
void PCIManager::check_all_buses()
{
if (get_header_type(0, 0, 0) & MULTI_FUNCTION)
{
for (int func = 0; func < 8 && get_vendor_id(0, 0, func) != INVALID; func++)
for (int func = 0; func < 8 && get_vendor_id(0, 0, func) != INVALID_VENDOR; func++)
check_bus(func);
}
else
@@ -94,9 +98,9 @@ namespace Kernel
}
}
void PCI::initialize_devices()
void PCIManager::initialize_devices()
{
for (const auto& pci_device : PCI::get().devices())
for (auto& pci_device : m_devices)
{
switch (pci_device.class_code())
{
@@ -134,7 +138,144 @@ namespace Kernel
}
}
PCIDevice::PCIDevice(uint8_t bus, uint8_t dev, uint8_t func)
BAN::ErrorOr<BAN::UniqPtr<BarRegion>> BarRegion::create(PCI::Device& device, uint8_t bar_num)
{
ASSERT(device.header_type() == 0x00);
uint32_t command_status = device.read_dword(0x04);
// disable io/mem space while reading bar
device.write_dword(0x04, command_status & ~3);
uint8_t offset = 0x10 + bar_num * 8;
uint64_t addr = device.read_dword(offset);
device.write_dword(offset, 0xFFFFFFFF);
uint32_t size = device.read_dword(0x10 + bar_num * 8);
size = ~size + 1;
device.write_dword(offset, addr);
// determine bar type
BarType type = BarType::INVALID;
if (addr & 1)
{
type = BarType::IO;
addr &= 0xFFFFFFFC;
}
else if ((addr & 0b110) == 0b000)
{
type = BarType::MEM;
addr &= 0xFFFFFFF0;
}
else if ((addr & 0b110) == 0b100)
{
type = BarType::MEM;
addr &= 0xFFFFFFF0;
addr |= (uint64_t)device.read_dword(offset + 8) << 32;
}
if (type == BarType::INVALID)
{
dwarnln("invalid pci device bar");
return BAN::Error::from_errno(EINVAL);
}
auto* region_ptr = new BarRegion(type, addr, size);
ASSERT(region_ptr);
auto region = BAN::UniqPtr<BarRegion>::adopt(region_ptr);
TRY(region->initialize());
// restore old command register and enable correct IO/MEM
command_status |= (type == BarType::IO) ? 1 : 2;
device.write_dword(0x04, command_status);
#if DEBUG_PCI
dprintln("created BAR region for PCI {}:{}.{}",
device.bus(),
device.dev(),
device.func()
);
dprintln(" type: {}", region->type() == BarType::IO ? "IO" : "MEM");
dprintln(" paddr {}", (void*)region->paddr());
dprintln(" vaddr {}", (void*)region->vaddr());
dprintln(" size {}", region->size());
#endif
return region;
}
BarRegion::BarRegion(BarType type, paddr_t paddr, size_t size)
: m_type(type)
, m_paddr(paddr)
, m_size(size)
{ }
BarRegion::~BarRegion()
{
if (m_type == BarType::MEM && m_vaddr)
PageTable::kernel().unmap_range(m_vaddr, m_size);
m_vaddr = 0;
}
BAN::ErrorOr<void> BarRegion::initialize()
{
if (m_type == BarType::IO)
return {};
size_t needed_pages = BAN::Math::div_round_up<size_t>(m_size, PAGE_SIZE);
m_vaddr = PageTable::kernel().reserve_free_contiguous_pages(needed_pages, KERNEL_OFFSET);
if (m_vaddr == 0)
return BAN::Error::from_errno(ENOMEM);
PageTable::kernel().map_range_at(m_paddr, m_vaddr, m_size, PageTable::Flags::CacheDisable | PageTable::Flags::ReadWrite | PageTable::Flags::Present);
return {};
}
void BarRegion::write8(off_t reg, uint8_t val)
{
if (m_type == BarType::IO)
return IO::outb(m_vaddr + reg, val);
MMIO::write8(m_vaddr + reg, val);
}
void BarRegion::write16(off_t reg, uint16_t val)
{
if (m_type == BarType::IO)
return IO::outw(m_vaddr + reg, val);
MMIO::write16(m_vaddr + reg, val);
}
void BarRegion::write32(off_t reg, uint32_t val)
{
if (m_type == BarType::IO)
return IO::outl(m_vaddr + reg, val);
MMIO::write32(m_vaddr + reg, val);
}
uint8_t BarRegion::read8(off_t reg)
{
if (m_type == BarType::IO)
return IO::inb(m_vaddr + reg);
return MMIO::read8(m_vaddr + reg);
}
uint16_t BarRegion::read16(off_t reg)
{
if (m_type == BarType::IO)
return IO::inw(m_vaddr + reg);
return MMIO::read16(m_vaddr + reg);
}
uint32_t BarRegion::read32(off_t reg)
{
if (m_type == BarType::IO)
return IO::inl(m_vaddr + reg);
return MMIO::read32(m_vaddr + reg);
}
PCI::Device::Device(uint8_t bus, uint8_t dev, uint8_t func)
: m_bus(bus), m_dev(dev), m_func(func)
{
uint32_t type = read_word(0x0A);
@@ -142,87 +283,92 @@ namespace Kernel
m_subclass = (uint8_t)(type);
m_prog_if = read_byte(0x09);
m_header_type = read_byte(0x0E);
enumerate_capabilites();
}
uint32_t PCIDevice::read_dword(uint8_t offset) const
uint32_t PCI::Device::read_dword(uint8_t offset) const
{
ASSERT((offset & 0x03) == 0);
return read_config_dword(m_bus, m_dev, m_func, offset);
}
uint16_t PCIDevice::read_word(uint8_t offset) const
uint16_t PCI::Device::read_word(uint8_t offset) const
{
ASSERT((offset & 0x01) == 0);
uint32_t dword = read_config_dword(m_bus, m_dev, m_func, offset & 0xFC);
return (uint16_t)(dword >> (8 * (offset & 0x03)));
}
uint8_t PCIDevice::read_byte(uint8_t offset) const
uint8_t PCI::Device::read_byte(uint8_t offset) const
{
uint32_t dword = read_config_dword(m_bus, m_dev, m_func, offset & 0xFC);
return (uint8_t)(dword >> (8 * (offset & 0x03)));
}
void PCIDevice::write_dword(uint8_t offset, uint32_t value) const
void PCI::Device::write_dword(uint8_t offset, uint32_t value)
{
ASSERT((offset & 0x03) == 0);
write_config_dword(m_bus, m_dev, m_func, offset, value);
}
PCIDevice::BarType PCIDevice::read_bar_type(uint8_t bar) const
BAN::ErrorOr<BAN::UniqPtr<BarRegion>> PCI::Device::allocate_bar_region(uint8_t bar_num)
{
ASSERT(m_header_type == 0x00);
ASSERT(bar <= 5);
uint32_t type = read_dword(0x10 + bar * 4) & 0b111;
if (type & 1)
return BarType::IO;
type >>= 1;
if (type == 0x0 || type == 0x2)
return BarType::MEM;
return BarType::INVAL;
return BarRegion::create(*this, bar_num);
}
uint64_t PCIDevice::read_bar_address(uint8_t bar) const
void PCI::Device::enumerate_capabilites()
{
ASSERT(m_header_type == 0x00);
ASSERT(bar <= 5);
uint16_t status = read_word(0x06);
if (!(status & (1 << 4)))
return;
uint64_t address = read_dword(0x10 + bar * 4);
if (address & 1)
return address & 0xFFFFFFFC;
if ((address & 0b110) == 0b100)
address |= (uint64_t)read_dword(0x10 + bar * 4 + 4) << 32;
return address & 0xFFFFFFFFFFFFFFF0;
uint8_t capabilities = read_byte(0x34) & 0xFC;
while (capabilities)
{
uint16_t next = read_word(capabilities);
dprintln(" cap {2H}", next & 0xFF);
capabilities = (next >> 8) & 0xFC;
}
}
void PCIDevice::enable_bus_mastering() const
void PCI::Device::enable_bus_mastering()
{
write_dword(0x04, read_dword(0x04) | 1u << 2);
}
void PCIDevice::disable_bus_mastering() const
void PCI::Device::disable_bus_mastering()
{
write_dword(0x04, read_dword(0x04) & ~(1u << 2));
}
void PCIDevice::enable_memory_space() const
void PCI::Device::enable_memory_space()
{
write_dword(0x04, read_dword(0x04) | 1u << 1);
}
void PCIDevice::disable_memory_space() const
void PCI::Device::disable_memory_space()
{
write_dword(0x04, read_dword(0x04) & ~(1u << 1));
}
void PCIDevice::enable_pin_interrupts() const
void PCI::Device::enable_io_space()
{
write_dword(0x04, read_dword(0x04) | 1u << 0);
}
void PCI::Device::disable_io_space()
{
write_dword(0x04, read_dword(0x04) & ~(1u << 0));
}
void PCI::Device::enable_pin_interrupts()
{
write_dword(0x04, read_dword(0x04) | 1u << 10);
}
void PCIDevice::disable_pin_interrupts() const
void PCI::Device::disable_pin_interrupts()
{
write_dword(0x04, read_dword(0x04) & ~(1u << 10));
}