Kernel: Rewrite HPET code
Now the set timer frequency actually works... :D
This commit is contained in:
parent
420a7b60ca
commit
00662bad46
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@ -6,10 +6,13 @@
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namespace Kernel
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{
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struct HPETRegisters;
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class HPET final : public Timer, public Interruptable
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{
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public:
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static BAN::ErrorOr<BAN::UniqPtr<HPET>> create(bool force_pic);
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~HPET();
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virtual uint64_t ms_since_boot() const override;
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virtual uint64_t ns_since_boot() const override;
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@ -21,11 +24,19 @@ namespace Kernel
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HPET() = default;
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BAN::ErrorOr<void> initialize(bool force_pic);
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void write_register(ptrdiff_t reg, uint64_t value) const;
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uint64_t read_register(ptrdiff_t reg) const;
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volatile HPETRegisters& registers();
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const volatile HPETRegisters& registers() const;
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uint64_t read_main_counter() const;
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private:
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uint64_t m_counter_tick_period_fs { 0 };
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bool m_is_64bit { false };
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uint64_t m_last_ticks { 0 };
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uint32_t m_32bit_wraps { 0 };
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uint32_t m_ticks_per_s { 0 };
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vaddr_t m_mmio_base { 0 };
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};
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@ -7,21 +7,7 @@
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#include <kernel/Scheduler.h>
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#include <kernel/Timer/HPET.h>
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#define HPET_REG_CAPABILIES 0x00
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#define HPET_REG_CONFIG 0x10
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#define HPET_REG_COUNTER 0xF0
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#define HPET_CONFIG_ENABLE 0x01
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#define HPET_CONFIG_LEG_RT 0x02
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#define HPET_REG_TIMER_CONFIG(N) (0x100 + 0x20 * N)
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#define HPET_REG_TIMER_COMPARATOR(N) (0x108 + 0x20 * N)
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#define HPET_Tn_INT_ENB_CNF (1 << 2)
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#define HPET_Tn_TYPE_CNF (1 << 3)
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#define HPET_Tn_PER_INT_CAP (1 << 4)
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#define HPET_Tn_VAL_SET_CNF (1 << 6)
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#define HPET_Tn_INT_ROUTE_CNF_SHIFT 9
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#define HPET_PERIOD_MAX 0x05F5E100
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#define FS_PER_S 1'000'000'000'000'000
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#define FS_PER_MS 1'000'000'000'000
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@ -31,17 +17,116 @@
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namespace Kernel
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{
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enum HPETCapabilities : uint32_t
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{
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LEG_RT_CAP = 1 << 16,
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COUNT_SIZE_CAP = 1 << 13,
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NUM_TIM_CAP_MASK = 0x1F << 8,
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NUM_TIM_CAP_SHIFT = 8,
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};
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enum HPETConfiguration : uint32_t
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{
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LEG_RT_CNF = 1 << 1,
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ENABLE_CNF = 1 << 0,
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};
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enum HPETTimerConfiguration : uint32_t
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{
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Tn_INT_TYPE_CNF = 1 << 1,
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Tn_INT_ENB_CNF = 1 << 2,
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Tn_TYPE_CNF = 1 << 3,
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Tn_PER_INT_CAP = 1 << 4,
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Tn_SIZE_CAP = 1 << 5,
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Tn_VAL_SET_CNF = 1 << 6,
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Tn_32MODE_CNF = 1 << 8,
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Tn_FSB_EN_CNF = 1 << 14,
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Tn_FSB_INT_DEL_CAP = 1 << 14,
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Tn_INT_ROUTE_CNF_MASK = 0x1F << 9,
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Tn_INT_ROUTE_CNF_SHIFT = 9,
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};
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struct HPETRegister
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{
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union
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{
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uint64_t full;
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struct
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{
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uint32_t low;
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uint32_t high;
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};
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};
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};
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static_assert(sizeof(HPETRegister) == 8);
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struct HPETTimer
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{
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uint32_t configuration;
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uint32_t int_route_cap;
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HPETRegister comparator;
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HPETRegister fsb_interrupt_route;
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uint64_t __reserved;
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};
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static_assert(sizeof(HPETTimer) == 32);
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struct HPETRegisters
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{
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/*
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63:32 COUNTER_CLK_PERIOD
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31:16 VENDOR_ID
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15 LEG_RT_CAP
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13 COUNT_SIZE_CAP
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12:8 NUM_TIM_CAP
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7:0 REV_ID
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*/
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uint32_t capabilities;
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uint32_t counter_clk_period;
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uint64_t __reserved0;
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/*
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1 LEG_RT_CNF
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0 ENABLE_CNF
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*/
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HPETRegister configuration;
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uint64_t __reserved1;
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/*
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N Tn_INT_STS
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*/
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HPETRegister interrupt_status;
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uint8_t __reserved2[0xF0 - 0x28];
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HPETRegister main_counter;
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uint64_t __reserved3;
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HPETTimer timers[32];
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};
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static_assert(offsetof(HPETRegisters, main_counter) == 0xF0);
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static_assert(offsetof(HPETRegisters, timers[0]) == 0x100);
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static_assert(offsetof(HPETRegisters, timers[1]) == 0x120);
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BAN::ErrorOr<BAN::UniqPtr<HPET>> HPET::create(bool force_pic)
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{
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HPET* hpet = new HPET();
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if (hpet == nullptr)
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HPET* hpet_ptr = new HPET();
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if (hpet_ptr == nullptr)
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return BAN::Error::from_errno(ENOMEM);
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if (auto ret = hpet->initialize(force_pic); ret.is_error())
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{
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delete hpet;
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return ret.release_error();
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}
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return BAN::UniqPtr<HPET>::adopt(hpet);
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auto hpet = BAN::UniqPtr<HPET>::adopt(hpet_ptr);
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TRY(hpet->initialize(force_pic));
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return hpet;
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}
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HPET::~HPET()
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{
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if (m_mmio_base)
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PageTable::kernel().unmap_page(m_mmio_base);
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m_mmio_base = 0;
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}
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BAN::ErrorOr<void> HPET::initialize(bool force_pic)
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@ -63,115 +148,155 @@ namespace Kernel
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ASSERT(m_mmio_base);
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PageTable::kernel().map_page_at(header->base_address.address, m_mmio_base, PageTable::Flags::ReadWrite | PageTable::Flags::Present);
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BAN::ScopeGuard unmapper([this] { PageTable::kernel().unmap_page(m_mmio_base); });
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m_counter_tick_period_fs = read_register(HPET_REG_CAPABILIES) >> 32;
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auto& regs = registers();
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// period has to be less than 100 ns
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if (m_counter_tick_period_fs == 0 || m_counter_tick_period_fs > FS_PER_NS * 100)
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return BAN::Error::from_errno(EINVAL);
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m_is_64bit = regs.capabilities & COUNT_SIZE_CAP;
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uint64_t ticks_per_ms = FS_PER_MS / m_counter_tick_period_fs;
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// Disable main counter and reset value
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regs.configuration.low = regs.configuration.low & ~ENABLE_CNF;
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regs.main_counter.high = 0;
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regs.main_counter.low = 0;
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// Enable legacy routing if available
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if (regs.capabilities & LEG_RT_CAP)
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regs.configuration.low = regs.configuration.low | LEG_RT_CNF;
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uint32_t period_fs = regs.counter_clk_period;
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if (period_fs == 0 || period_fs > HPET_PERIOD_MAX)
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{
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const char* units[] = { "fs", "ps", "ns" };
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int index = 0;
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uint64_t temp = m_counter_tick_period_fs;
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while (temp >= 1000)
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{
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temp /= 1000;
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index++;
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}
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dprintln("HPET percision {} {}", temp, units[index]);
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dwarnln("HPET: Invalid counter period");
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return BAN::Error::from_errno(EINVAL);
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}
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uint64_t timer0_config = read_register(HPET_REG_TIMER_CONFIG(0));
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if (!(timer0_config & HPET_Tn_PER_INT_CAP))
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m_ticks_per_s = FS_PER_S / period_fs;
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dprintln("HPET frequency {} Hz", m_ticks_per_s);
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uint8_t last_timer = (regs.capabilities & NUM_TIM_CAP_MASK) >> NUM_TIM_CAP_SHIFT;
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dprintln("HPET has {} timers", last_timer + 1);
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// Disable all timers
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for (uint8_t i = 0; i <= last_timer; i++)
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{
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dwarnln("timer 0 doesn't support periodic");
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auto& timer_regs = regs.timers[i];
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timer_regs.configuration = timer_regs.configuration & ~Tn_INT_ENB_CNF;
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}
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auto& timer0 = regs.timers[0];
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if (!(timer0.configuration & Tn_PER_INT_CAP))
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{
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dwarnln("HPET: timer0 cannot be periodic");
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return BAN::Error::from_errno(ENOTSUP);
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}
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int irq = 0;
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if (!force_pic)
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// enable interrupts
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timer0.configuration = timer0.configuration | Tn_INT_ENB_CNF;
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// clear interrupt mask (set irq to 0)
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timer0.configuration = timer0.configuration & ~Tn_INT_ROUTE_CNF_MASK;
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// edge triggered interrupts
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timer0.configuration = timer0.configuration & ~Tn_INT_TYPE_CNF;
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// periodic timer
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timer0.configuration = timer0.configuration | Tn_TYPE_CNF;
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// disable 32 bit mode
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timer0.configuration = timer0.configuration & ~Tn_32MODE_CNF;
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// disable FSB interrupts
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if (timer0.configuration & Tn_FSB_INT_DEL_CAP)
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timer0.configuration = timer0.configuration & ~Tn_FSB_EN_CNF;
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// set timer period to 1000 Hz
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uint64_t ticks_per_ms = m_ticks_per_s / 1000;
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timer0.configuration = timer0.configuration | Tn_VAL_SET_CNF;
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timer0.comparator.low = ticks_per_ms;
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if (timer0.configuration & Tn_SIZE_CAP)
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{
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uint32_t irq_cap = timer0_config >> 32;
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if (irq_cap == 0)
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{
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dwarnln("HPET doesn't have any interrupts available");
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return BAN::Error::from_errno(EINVAL);
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}
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for (irq = 0; irq < 32; irq++)
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if (irq_cap & (1 << irq))
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break;
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timer0.configuration = timer0.configuration | Tn_VAL_SET_CNF;
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timer0.comparator.high = ticks_per_ms >> 32;
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}
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else if (ticks_per_ms > 0xFFFFFFFF)
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{
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dprintln("HPET: cannot create 1 kHz timer");
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return BAN::Error::from_errno(ENOTSUP);
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}
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TRY(InterruptController::get().reserve_irq(irq));
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unmapper.disable();
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// enable main counter
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regs.configuration.low = regs.configuration.low | ENABLE_CNF;
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uint64_t main_flags = HPET_CONFIG_ENABLE;
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if (force_pic)
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main_flags |= HPET_CONFIG_LEG_RT;
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// Enable main counter
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write_register(HPET_REG_CONFIG, read_register(HPET_REG_CONFIG) | main_flags);
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uint64_t timer0_flags = 0;
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timer0_flags |= HPET_Tn_INT_ENB_CNF;
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timer0_flags |= HPET_Tn_TYPE_CNF;
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timer0_flags |= HPET_Tn_VAL_SET_CNF;
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if (!force_pic)
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timer0_flags |= irq << HPET_Tn_INT_ROUTE_CNF_SHIFT;
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// Enable timer 0 as 1 ms periodic
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write_register(HPET_REG_TIMER_CONFIG(0), timer0_flags);
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write_register(HPET_REG_TIMER_COMPARATOR(0), read_register(HPET_REG_COUNTER) + ticks_per_ms);
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write_register(HPET_REG_TIMER_COMPARATOR(0), ticks_per_ms);
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// Disable timers 1->
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for (int i = 1; i <= header->comparator_count; i++)
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write_register(HPET_REG_TIMER_CONFIG(i), 0);
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set_irq(irq);
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TRY(InterruptController::get().reserve_irq(0));
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set_irq(0);
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enable_interrupt();
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return {};
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}
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volatile HPETRegisters& HPET::registers()
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{
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return *reinterpret_cast<volatile HPETRegisters*>(m_mmio_base);
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}
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const volatile HPETRegisters& HPET::registers() const
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{
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return *reinterpret_cast<const volatile HPETRegisters*>(m_mmio_base);
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}
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uint64_t HPET::read_main_counter() const
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{
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auto& regs = registers();
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if (m_is_64bit)
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return regs.main_counter.full;
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uint32_t current = regs.main_counter.low;
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uint64_t wraps = m_32bit_wraps;
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if (current < (uint32_t)m_last_ticks)
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wraps++;
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return (wraps << 32) | current;
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}
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void HPET::handle_irq()
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{
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auto& regs = registers();
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uint64_t current_ticks { 0 };
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if (m_is_64bit)
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current_ticks = regs.main_counter.full;
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else
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{
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uint32_t current = regs.main_counter.low;
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if (current < (uint32_t)m_last_ticks)
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m_32bit_wraps++;
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current_ticks = ((uint64_t)m_32bit_wraps << 32) | current;
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}
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m_last_ticks = current_ticks;
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Scheduler::get().timer_reschedule();
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}
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uint64_t HPET::ms_since_boot() const
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{
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// FIXME: 32 bit CPUs should use 32 bit counter with 32 bit reads
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return read_register(HPET_REG_COUNTER) * m_counter_tick_period_fs / FS_PER_MS;
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return ns_since_boot() / 1'000'000;
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}
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uint64_t HPET::ns_since_boot() const
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{
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// FIXME: 32 bit CPUs should use 32 bit counter with 32 bit reads
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return read_register(HPET_REG_COUNTER) * m_counter_tick_period_fs / FS_PER_NS;
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auto current = time_since_boot();
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return current.tv_sec * 1'000'000'000 + current.tv_nsec;
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}
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timespec HPET::time_since_boot() const
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{
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uint64_t time_fs = read_register(HPET_REG_COUNTER) * m_counter_tick_period_fs;
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auto& regs = registers();
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uint64_t counter = read_main_counter();
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uint64_t seconds = counter / m_ticks_per_s;
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uint64_t ticks_this_second = counter % m_ticks_per_s;
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long ns_this_second = ticks_this_second * regs.counter_clk_period / FS_PER_NS;
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return timespec {
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.tv_sec = time_fs / FS_PER_S,
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.tv_nsec = (long)((time_fs % FS_PER_S) / FS_PER_NS)
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.tv_sec = seconds,
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.tv_nsec = ns_this_second
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};
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}
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void HPET::write_register(ptrdiff_t reg, uint64_t value) const
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{
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MMIO::write64(m_mmio_base + reg, value);
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}
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uint64_t HPET::read_register(ptrdiff_t reg) const
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{
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return MMIO::read64(m_mmio_base + reg);
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}
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}
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