I had not understood how MSIs work and I was unnecessarily routing them
through IOAPIC. This is not necessary and should not be done :D
Also MSIs were reserving interrupts that IOAPIC was capable of
generating. Now IOAPIC and MSIs use different set of interrupts so
IOAPIC can use more interrupts if needed.
This makes scheduler preemption much cleaner as bsb does not have to
send smp messages to notify other processes about timer interrupt.
Also PIT percision is now "full" 0.8 us instead of 1 ms that I was using
before.
Also move the spin wait to check for pending IPI sends to the start of
ipi sending function. There is no need to wait for IPI send succeeding
right after it. It is enough to make sure there are not multiple IPIs
being sent at the same time.
Bananymous
Bananymous