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Kernel: All processors use LAPIC timer when running with APIC

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This makes scheduler preemption much cleaner as bsb does not have to
send smp messages to notify other processes about timer interrupt.

Also PIT percision is now "full" 0.8 us instead of 1 ms that I was using
before.
This commit is contained in:
Bananymous
2024-07-23 02:28:52 +03:00
parent 3e0150f847
commit 539afb329a
17 changed files with 224 additions and 73 deletions
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9
kernel/kernel/IDT.cpp
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@@ -333,6 +333,13 @@ done:
Processor::handle_ipi();
}
extern "C" void cpp_timer_handler()
{
ASSERT(InterruptController::get().is_in_service(IRQ_TIMER));
InterruptController::get().eoi(IRQ_TIMER);
Processor::scheduler().timer_interrupt();
}
extern "C" void cpp_irq_handler(uint32_t irq)
{
if (g_paniced)
@@ -409,6 +416,7 @@ done:
extern "C" void asm_yield_handler();
extern "C" void asm_ipi_handler();
extern "C" void asm_timer_handler();
extern "C" void asm_syscall_handler();
IDT* IDT::create()
@@ -428,6 +436,7 @@ done:
idt->register_interrupt_handler(IRQ_VECTOR_BASE + IRQ_YIELD, asm_yield_handler);
idt->register_interrupt_handler(IRQ_VECTOR_BASE + IRQ_IPI, asm_ipi_handler);
idt->register_interrupt_handler(IRQ_VECTOR_BASE + IRQ_TIMER, asm_timer_handler);
idt->register_syscall_handler(0x80, asm_syscall_handler);