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banan-os/kernel/arch/x86_64/IDT.cpp

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Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
2023-01-25 19:05:47 +02:00
#include <BAN/Errors.h>
#include <kernel/IDT.h>
#include <kernel/InterruptController.h>
#include <kernel/kmalloc.h>
#include <kernel/Panic.h>
#define REGISTER_ISR_HANDLER(i) register_interrupt_handler(i, isr ## i)
#define REGISTER_IRQ_HANDLER(i) register_interrupt_handler(IRQ_VECTOR_BASE + i, irq ## i)
namespace IDT
{
Kernel: Add actual register values to x86_64 kernel panic Very hackish implementation, but we now get actual registers at the time of the interrupt happening
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struct Registers
{
uint64_t rsp;
uint64_t rip;
uint64_t rflags;
uint64_t cr4;
uint64_t cr3;
uint64_t cr2;
uint64_t cr0;
uint64_t r15;
uint64_t r14;
uint64_t r13;
uint64_t r12;
uint64_t r11;
uint64_t r10;
uint64_t r9;
uint64_t r8;
uint64_t rsi;
uint64_t rdi;
uint64_t rbp;
uint64_t rdx;
uint64_t rcx;
uint64_t rbx;
uint64_t rax;
};
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
2023-01-25 19:05:47 +02:00
struct GateDescriptor
{
uint16_t offset1;
uint16_t selector;
uint8_t IST;
uint8_t flags;
uint16_t offset2;
uint32_t offset3;
uint32_t reserved;
} __attribute__((packed));
struct IDTR
{
uint16_t size;
uint64_t offset;
} __attribute__((packed));
static IDTR s_idtr;
static GateDescriptor* s_idt = nullptr;
Kernel: I have no idea what this commit does I had committed a change in IDT but reverted it now. This propably only adds a spurious interrupt detection to common cpp interrupt handler?
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static void(*s_irq_handlers[0x10])() { nullptr };
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
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static const char* isr_exceptions[] =
{
"Division Error",
"Debug",
"Non-maskable Interrupt",
"Breakpoint",
"Overflow",
"Bound Range Exception",
"Invalid Opcode",
"Device Not Available",
"Double Fault",
"Coprocessor Segment Overrun",
"Invalid TSS",
"Segment Not Present",
"Stack-Segment Fault",
"General Protection Fault",
"Page Fault",
"Unknown Exception 0x0F",
"x87 Floating-Point Exception",
"Alignment Check",
"Machine Check",
"SIMD Floating-Point Exception",
"Virtualization Exception",
"Control Protection Exception",
"Unknown Exception 0x16",
"Unknown Exception 0x17",
"Unknown Exception 0x18",
"Unknown Exception 0x19",
"Unknown Exception 0x1A",
"Unknown Exception 0x1B",
"Hypervisor Injection Exception",
"VMM Communication Exception",
"Security Exception",
"Unkown Exception 0x1F",
};
Kernel: Add actual register values to x86_64 kernel panic Very hackish implementation, but we now get actual registers at the time of the interrupt happening
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extern "C" void cpp_isr_handler(uint64_t isr, uint64_t error, const Registers* regs)
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
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{
All: rename every function from UpperCamelCase to snake_case This was a mess since I didn't know which to use but now I decided to go with snake_case :)
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Kernel::panic(
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
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"{} (error code: 0x{16H})\r\n"
"Register dump\r\n"
"rax=0x{16H}, rbx=0x{16H}, rcx=0x{16H}, rdx=0x{16H}\r\n"
Kernel: Add actual register values to x86_64 kernel panic Very hackish implementation, but we now get actual registers at the time of the interrupt happening
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"rsp=0x{16H}, rbp=0x{16H}, rdi=0x{16H}, rsi=0x{16H}\r\n"
"rip=0x{16H}, rflags=0x{16H}\r\n"
"cr0=0x{16H}, cr2=0x{16H}, cr3=0x{16H}, cr4=0x{16H}\r\n",
isr_exceptions[isr], error,
regs->rax, regs->rbx, regs->rcx, regs->rdx,
regs->rsp, regs->rbp, regs->rdi, regs->rsi,
regs->rip, regs->rflags,
regs->cr0, regs->cr2, regs->cr3, regs->cr4
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
2023-01-25 19:05:47 +02:00
);
}
extern "C" void cpp_irq_handler(uint64_t irq)
{
if (s_irq_handlers[irq])
s_irq_handlers[irq]();
else
Kernel: I have no idea what this commit does I had committed a change in IDT but reverted it now. This propably only adds a spurious interrupt detection to common cpp interrupt handler?
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{
All: rename every function from UpperCamelCase to snake_case This was a mess since I didn't know which to use but now I decided to go with snake_case :)
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if (!InterruptController::get().is_in_service(irq))
Kernel: I have no idea what this commit does I had committed a change in IDT but reverted it now. This propably only adds a spurious interrupt detection to common cpp interrupt handler?
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{
dprintln("spurious irq 0x{2H}", irq);
return;
}
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
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dprintln("no handler for irq 0x{2H}\n", irq);
Kernel: I have no idea what this commit does I had committed a change in IDT but reverted it now. This propably only adds a spurious interrupt detection to common cpp interrupt handler?
2023-01-25 22:15:32 +02:00
}
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
2023-01-25 19:05:47 +02:00
Kernel: Sleep now actually sleeps and allows idling
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// NOTE: Scheduler sends PIT eoi's
if (irq != PIT_IRQ)
InterruptController::get().eoi(irq);
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
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}
static void flush_idt()
{
asm volatile("lidt %0"::"m"(s_idtr));
}
Kernel: Add actual register values to x86_64 kernel panic Very hackish implementation, but we now get actual registers at the time of the interrupt happening
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static void register_interrupt_handler(uint8_t index, void(*handler)())
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
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{
GateDescriptor& descriptor = s_idt[index];
Kernel: Add actual register values to x86_64 kernel panic Very hackish implementation, but we now get actual registers at the time of the interrupt happening
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descriptor.offset1 = (uint16_t)((uint64_t)handler >> 0);
descriptor.offset2 = (uint16_t)((uint64_t)handler >> 16);
descriptor.offset3 = (uint32_t)((uint64_t)handler >> 32);
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
2023-01-25 19:05:47 +02:00
descriptor.selector = 0x08;
descriptor.IST = 0;
descriptor.flags = 0x8E;
}
Kernel: Add actual register values to x86_64 kernel panic Very hackish implementation, but we now get actual registers at the time of the interrupt happening
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void register_irq_handler(uint8_t irq, void(*handler)())
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
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{
Kernel: Add actual register values to x86_64 kernel panic Very hackish implementation, but we now get actual registers at the time of the interrupt happening
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s_irq_handlers[irq] = handler;
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
2023-01-25 19:05:47 +02:00
}
extern "C" void isr0();
extern "C" void isr1();
extern "C" void isr2();
extern "C" void isr3();
extern "C" void isr4();
extern "C" void isr5();
extern "C" void isr6();
extern "C" void isr7();
extern "C" void isr8();
extern "C" void isr9();
extern "C" void isr10();
extern "C" void isr11();
extern "C" void isr12();
extern "C" void isr13();
extern "C" void isr14();
extern "C" void isr15();
extern "C" void isr16();
extern "C" void isr17();
extern "C" void isr18();
extern "C" void isr19();
extern "C" void isr20();
extern "C" void isr21();
extern "C" void isr22();
extern "C" void isr23();
extern "C" void isr24();
extern "C" void isr25();
extern "C" void isr26();
extern "C" void isr27();
extern "C" void isr28();
extern "C" void isr29();
extern "C" void isr30();
extern "C" void isr31();
extern "C" void irq0();
extern "C" void irq1();
extern "C" void irq2();
extern "C" void irq3();
extern "C" void irq4();
extern "C" void irq5();
extern "C" void irq6();
extern "C" void irq7();
extern "C" void irq8();
extern "C" void irq9();
extern "C" void irq10();
extern "C" void irq11();
extern "C" void irq12();
extern "C" void irq13();
extern "C" void irq14();
extern "C" void irq15();
void initialize()
{
Kernel: rewrite the whole kmalloc (again) Performance of the old kmalloc implementation was terrible. We now use fixed-width linked list allocations for sizes <= 60 bytes. This is much faster than variable size allocation. We don't use bitmap scanning anymore since it was probably the slow part. Instead we use headers that tell allocations size and aligment. I removed the kmalloc_eternal, even though it was very fast, there is not really any need for it, since the only place it was used in was IDT. These changes allowed my psf (font) parsing to go from ~500 ms to ~20 ms. (coming soon :D)
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s_idt = (GateDescriptor*)kmalloc(0x100 * sizeof(GateDescriptor));
Kernel: IDT now confirms that it allocated succesfully
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ASSERT(s_idt);
Kernel: Finally managed to get 64-bit working I had weird problems with interrupts but everything should work now
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memset(s_idt, 0x00, 0x100 * sizeof(GateDescriptor));
s_idtr.offset = (uint64_t)s_idt;
s_idtr.size = 0x100 * sizeof(GateDescriptor) - 1;
REGISTER_ISR_HANDLER(0);
REGISTER_ISR_HANDLER(1);
REGISTER_ISR_HANDLER(2);
REGISTER_ISR_HANDLER(3);
REGISTER_ISR_HANDLER(4);
REGISTER_ISR_HANDLER(5);
REGISTER_ISR_HANDLER(6);
REGISTER_ISR_HANDLER(7);
REGISTER_ISR_HANDLER(8);
REGISTER_ISR_HANDLER(9);
REGISTER_ISR_HANDLER(10);
REGISTER_ISR_HANDLER(11);
REGISTER_ISR_HANDLER(12);
REGISTER_ISR_HANDLER(13);
REGISTER_ISR_HANDLER(14);
REGISTER_ISR_HANDLER(15);
REGISTER_ISR_HANDLER(16);
REGISTER_ISR_HANDLER(17);
REGISTER_ISR_HANDLER(18);
REGISTER_ISR_HANDLER(19);
REGISTER_ISR_HANDLER(20);
REGISTER_ISR_HANDLER(21);
REGISTER_ISR_HANDLER(22);
REGISTER_ISR_HANDLER(23);
REGISTER_ISR_HANDLER(24);
REGISTER_ISR_HANDLER(25);
REGISTER_ISR_HANDLER(26);
REGISTER_ISR_HANDLER(27);
REGISTER_ISR_HANDLER(28);
REGISTER_ISR_HANDLER(29);
REGISTER_ISR_HANDLER(30);
REGISTER_ISR_HANDLER(31);
REGISTER_IRQ_HANDLER(0);
REGISTER_IRQ_HANDLER(1);
REGISTER_IRQ_HANDLER(2);
REGISTER_IRQ_HANDLER(3);
REGISTER_IRQ_HANDLER(4);
REGISTER_IRQ_HANDLER(5);
REGISTER_IRQ_HANDLER(6);
REGISTER_IRQ_HANDLER(7);
REGISTER_IRQ_HANDLER(8);
REGISTER_IRQ_HANDLER(9);
REGISTER_IRQ_HANDLER(10);
REGISTER_IRQ_HANDLER(11);
REGISTER_IRQ_HANDLER(12);
REGISTER_IRQ_HANDLER(13);
REGISTER_IRQ_HANDLER(14);
REGISTER_IRQ_HANDLER(15);
flush_idt();
}
}