forked from Bananymous/banan-os
375 lines
9.1 KiB
C++
375 lines
9.1 KiB
C++
#include <kernel/IDT.h>
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#include <kernel/InterruptController.h>
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#include <kernel/IO.h>
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#include <kernel/Memory/PageTable.h>
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#include <kernel/MMIO.h>
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#include <kernel/Networking/E1000.h>
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#define DEBUG_E1000 1
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#define E1000_REG_CTRL 0x0000
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#define E1000_REG_STATUS 0x0008
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#define E1000_REG_EEPROM 0x0014
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#define E1000_REG_INT_CAUSE_READ 0x00C0
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#define E1000_REG_INT_RATE 0x00C4
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#define E1000_REG_INT_MASK_SET 0x00D0
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#define E1000_REG_INT_MASK_CLEAR 0x00D8
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#define E1000_REG_RCTRL 0x0100
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#define E1000_REG_RXDESCLO 0x2800
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#define E1000_REG_RXDESCHI 0x2804
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#define E1000_REG_RXDESCLEN 0x2808
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#define E1000_REG_RXDESCHEAD 0x2810
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#define E1000_REG_RXDESCTAIL 0x2818
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#define E1000_REG_TXDESCLO 0x3800
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#define E1000_REG_TXDESCHI 0x3804
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#define E1000_REG_TXDESCLEN 0x3808
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#define E1000_REG_TXDESCHEAD 0x3810
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#define E1000_REG_TXDESCTAIL 0x3818
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#define E1000_REG_TCTRL 0x0400
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#define E1000_REG_TIPG 0x0410
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#define E1000_STATUS_LINK_UP 0x02
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#define E1000_STATUS_SPEED_MASK 0xC0
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#define E1000_STATUS_SPEED_10MB 0x00
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#define E1000_STATUS_SPEED_100MB 0x40
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#define E1000_STATUS_SPEED_1000MB1 0x80
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#define E1000_STATUS_SPEED_1000MB2 0xC0
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#define E1000_CTRL_SET_LINK_UP 0x40
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#define E1000_INT_TXDW (1 << 0)
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#define E1000_INT_TXQE (1 << 1)
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#define E1000_INT_LSC (1 << 2)
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#define E1000_INT_RXSEQ (1 << 3)
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#define E1000_INT_RXDMT0 (1 << 4)
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#define E1000_INT_RXO (1 << 6)
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#define E1000_INT_RXT0 (1 << 7)
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#define E1000_INT_MDAC (1 << 9)
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#define E1000_INT_RXCFG (1 << 10)
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#define E1000_INT_PHYINT (1 << 12)
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#define E1000_INT_TXD_LOW (1 << 15)
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#define E1000_INT_SRPD (1 << 16)
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#define E1000_TCTL_EN (1 << 1)
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#define E1000_TCTL_PSP (1 << 3)
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#define E1000_TCTL_CT_SHIFT 4
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#define E1000_TCTL_COLD_SHIFT 12
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#define E1000_TCTL_SWXOFF (1 << 22)
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#define E1000_TCTL_RTLC (1 << 24)
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#define E1000_RCTL_EN (1 << 1)
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#define E1000_RCTL_SBP (1 << 2)
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#define E1000_RCTL_UPE (1 << 3)
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#define E1000_RCTL_MPE (1 << 4)
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#define E1000_RCTL_LPE (1 << 5)
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#define E1000_RCTL_LBM_NONE (0 << 6)
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#define E1000_RCTL_LBM_PHY (3 << 6)
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#define E1000_RTCL_RDMTS_HALF (0 << 8)
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#define E1000_RTCL_RDMTS_QUARTER (1 << 8)
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#define E1000_RTCL_RDMTS_EIGHTH (2 << 8)
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#define E1000_RCTL_MO_36 (0 << 12)
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#define E1000_RCTL_MO_35 (1 << 12)
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#define E1000_RCTL_MO_34 (2 << 12)
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#define E1000_RCTL_MO_32 (3 << 12)
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#define E1000_RCTL_BAM (1 << 15)
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#define E1000_RCTL_VFE (1 << 18)
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#define E1000_RCTL_CFIEN (1 << 19)
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#define E1000_RCTL_CFI (1 << 20)
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#define E1000_RCTL_DPF (1 << 22)
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#define E1000_RCTL_PMCF (1 << 23)
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#define E1000_RCTL_SECRC (1 << 26)
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#define E1000_RCTL_BSIZE_256 (3 << 16)
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#define E1000_RCTL_BSIZE_512 (2 << 16)
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#define E1000_RCTL_BSIZE_1024 (1 << 16)
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#define E1000_RCTL_BSIZE_2048 (0 << 16)
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#define E1000_RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
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#define E1000_RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
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#define E1000_RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
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namespace Kernel
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{
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struct e1000_rx_desc
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{
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volatile uint64_t addr;
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volatile uint16_t length;
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volatile uint16_t checksum;
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volatile uint8_t status;
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volatile uint8_t errors;
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volatile uint16_t special;
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} __attribute__((packed));
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struct e1000_tx_desc
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{
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volatile uint64_t addr;
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volatile uint16_t length;
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volatile uint8_t cso;
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volatile uint8_t cmd;
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volatile uint8_t status;
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volatile uint8_t css;
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volatile uint16_t special;
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} __attribute__((packed));
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// https://www.intel.com/content/dam/doc/manual/pci-pci-x-family-gbe-controllers-software-dev-manual.pdf (section 5.2)
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bool E1000::probe(PCI::Device& pci_device)
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{
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// Intel device
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if (pci_device.vendor_id() != 0x8086)
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return false;
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switch (pci_device.device_id())
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{
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case 0x1019:
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case 0x101A:
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case 0x1010:
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case 0x1012:
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case 0x101D:
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case 0x1079:
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case 0x107A:
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case 0x107B:
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case 0x100F:
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case 0x1011:
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case 0x1026:
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case 0x1027:
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case 0x1028:
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case 0x1107:
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case 0x1112:
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case 0x1013:
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case 0x1018:
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case 0x1076:
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case 0x1077:
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case 0x1078:
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case 0x1017:
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case 0x1016:
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case 0x100e:
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case 0x1015:
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return true;
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default:
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return false;
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}
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}
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BAN::ErrorOr<BAN::UniqPtr<E1000>> E1000::create(PCI::Device& pci_device)
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{
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E1000* e1000 = new E1000();
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ASSERT(e1000);
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if (auto ret = e1000->initialize(pci_device); ret.is_error())
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{
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delete e1000;
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return ret.release_error();
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}
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return BAN::UniqPtr<E1000>::adopt(e1000);
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}
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E1000::~E1000()
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{
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}
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BAN::ErrorOr<void> E1000::initialize(PCI::Device& pci_device)
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{
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m_bar_region = TRY(pci_device.allocate_bar_region(0));
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pci_device.enable_bus_mastering();
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detect_eeprom();
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TRY(read_mac_address());
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initialize_rx();
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initialize_tx();
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enable_link();
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enable_interrupts();
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#if DEBUG_E1000
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dprintln("E1000 at PCI {}:{}.{}", pci_device.bus(), pci_device.dev(), pci_device.func());
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dprintln(" MAC: {2H}:{2H}:{2H}:{2H}:{2H}:{2H}",
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m_mac_address[0],
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m_mac_address[1],
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m_mac_address[2],
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m_mac_address[3],
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m_mac_address[4],
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m_mac_address[5]
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);
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dprintln(" link up: {}", link_up());
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if (link_up())
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dprintln(" link speed: {} Mbps", link_speed());
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#endif
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return {};
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}
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void E1000::write32(uint16_t reg, uint32_t value)
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{
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m_bar_region->write32(reg, value);
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}
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uint32_t E1000::read32(uint16_t reg)
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{
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return m_bar_region->read32(reg);
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}
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void E1000::detect_eeprom()
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{
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m_has_eerprom = false;
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write32(E1000_REG_EEPROM, 0x01);
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for (int i = 0; i < 1000 && !m_has_eerprom; i++)
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if (read32(E1000_REG_EEPROM) & 0x10)
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m_has_eerprom = true;
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}
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uint32_t E1000::eeprom_read(uint8_t address)
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{
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uint32_t tmp = 0;
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if (m_has_eerprom)
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{
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write32(E1000_REG_EEPROM, ((uint32_t)address << 8) | 1);
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while (!((tmp = read32(E1000_REG_EEPROM)) & (1 << 4)))
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continue;
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}
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else
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{
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write32(E1000_REG_EEPROM, ((uint32_t)address << 2) | 1);
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while (!((tmp = read32(E1000_REG_EEPROM)) & (1 << 1)))
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continue;
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}
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return (tmp >> 16) & 0xFFFF;
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}
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BAN::ErrorOr<void> E1000::read_mac_address()
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{
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if (m_has_eerprom)
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{
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uint32_t temp = eeprom_read(0);
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m_mac_address[0] = temp;
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m_mac_address[1] = temp >> 8;
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temp = eeprom_read(1);
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m_mac_address[2] = temp;
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m_mac_address[3] = temp >> 8;
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temp = eeprom_read(2);
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m_mac_address[4] = temp;
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m_mac_address[5] = temp >> 8;
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return {};
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}
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if (read32(0x5400) == 0)
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{
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dwarnln("no mac address");
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return BAN::Error::from_errno(EINVAL);
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}
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for (int i = 0; i < 6; i++)
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m_mac_address[i] = (uint8_t)read32(0x5400 + i * 8);
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return {};
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}
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void E1000::initialize_rx()
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{
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uint8_t* ptr = (uint8_t*)kmalloc(sizeof(e1000_rx_desc) * E1000_NUM_RX_DESC + 16, 16, true);
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ASSERT(ptr);
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e1000_rx_desc* descs = (e1000_rx_desc*)ptr;
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for (int i = 0; i < E1000_NUM_RX_DESC; i++)
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{
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// FIXME
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m_rx_descs[i] = &descs[i];
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m_rx_descs[i]->addr = 0;
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m_rx_descs[i]->status = 0;
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}
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write32(E1000_REG_RXDESCLO, (uintptr_t)ptr >> 32);
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write32(E1000_REG_RXDESCHI, (uintptr_t)ptr & 0xFFFFFFFF);
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write32(E1000_REG_RXDESCLEN, E1000_NUM_RX_DESC * sizeof(e1000_rx_desc));
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write32(E1000_REG_RXDESCHEAD, 0);
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write32(E1000_REG_RXDESCTAIL, E1000_NUM_RX_DESC - 1);
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m_rx_current = 0;
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uint32_t rctrl = 0;
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rctrl |= E1000_RCTL_EN;
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rctrl |= E1000_RCTL_SBP;
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rctrl |= E1000_RCTL_UPE;
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rctrl |= E1000_RCTL_MPE;
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rctrl |= E1000_RCTL_LBM_NONE;
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rctrl |= E1000_RTCL_RDMTS_HALF;
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rctrl |= E1000_RCTL_BAM;
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rctrl |= E1000_RCTL_SECRC;
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rctrl |= E1000_RCTL_BSIZE_8192;
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write32(E1000_REG_RCTRL, rctrl);
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}
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void E1000::initialize_tx()
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{
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auto* ptr = (uint8_t*)kmalloc(sizeof(e1000_tx_desc) * E1000_NUM_TX_DESC + 16, 16, true);
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ASSERT(ptr);
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auto* descs = (e1000_tx_desc*)ptr;
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for(int i = 0; i < E1000_NUM_TX_DESC; i++)
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{
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// FIXME
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m_tx_descs[i] = &descs[i];
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m_tx_descs[i]->addr = 0;
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m_tx_descs[i]->cmd = 0;
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}
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write32(E1000_REG_TXDESCHI, (uintptr_t)ptr >> 32);
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write32(E1000_REG_TXDESCLO, (uintptr_t)ptr & 0xFFFFFFFF);
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write32(E1000_REG_TXDESCLEN, E1000_NUM_TX_DESC * sizeof(e1000_tx_desc));
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write32(E1000_REG_TXDESCHEAD, 0);
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write32(E1000_REG_TXDESCTAIL, 0);
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m_tx_current = 0;
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write32(E1000_REG_TCTRL, read32(E1000_REG_TCTRL) | E1000_TCTL_EN | E1000_TCTL_PSP);
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write32(E1000_REG_TIPG, 0x0060200A);
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}
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void E1000::enable_link()
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{
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write32(E1000_REG_CTRL, read32(E1000_REG_CTRL) | E1000_CTRL_SET_LINK_UP);
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m_link_up = !!(read32(E1000_REG_STATUS) & E1000_STATUS_LINK_UP);
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}
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int E1000::link_speed()
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{
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if (!link_up())
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return 0;
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uint32_t speed = read32(E1000_REG_STATUS) & E1000_STATUS_SPEED_MASK;
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if (speed == E1000_STATUS_SPEED_10MB)
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return 10;
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if (speed == E1000_STATUS_SPEED_100MB)
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return 100;
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if (speed == E1000_STATUS_SPEED_1000MB1)
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return 1000;
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if (speed == E1000_STATUS_SPEED_1000MB2)
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return 1000;
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return 0;
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}
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void E1000::enable_interrupts()
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{
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write32(E1000_REG_INT_RATE, 6000);
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write32(E1000_REG_INT_MASK_SET, E1000_INT_LSC | E1000_INT_RXT0 | E1000_INT_RXO);
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read32(E1000_REG_INT_CAUSE_READ);
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// FIXME: implement PCI interrupt allocation
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//IDT::register_irq_handler(irq, E1000::interrupt_handler);
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//InterruptController::enable_irq(irq);
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}
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BAN::ErrorOr<void> E1000::send_packet(const void* data, uint16_t len)
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{
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(void)data;
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(void)len;
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return BAN::Error::from_errno(ENOTSUP);
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}
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}
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