forked from Bananymous/banan-os
268 lines
6.2 KiB
C++
268 lines
6.2 KiB
C++
#include <BAN/Errors.h>
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#include <kernel/IDT.h>
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#include <kernel/InterruptController.h>
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#include <kernel/kmalloc.h>
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#include <kernel/Panic.h>
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#define REGISTER_ISR_HANDLER(i) register_interrupt_handler(i, isr ## i)
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#define REGISTER_IRQ_HANDLER(i) register_interrupt_handler(IRQ_VECTOR_BASE + i, irq ## i)
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namespace IDT
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{
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struct Registers
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{
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uint64_t rsp;
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uint64_t rip;
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uint64_t rflags;
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uint64_t cr4;
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uint64_t cr3;
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uint64_t cr2;
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uint64_t cr0;
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uint64_t r15;
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uint64_t r14;
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uint64_t r13;
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uint64_t r12;
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uint64_t r11;
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uint64_t r10;
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uint64_t r9;
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uint64_t r8;
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uint64_t rsi;
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uint64_t rdi;
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uint64_t rbp;
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uint64_t rdx;
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uint64_t rcx;
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uint64_t rbx;
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uint64_t rax;
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};
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struct GateDescriptor
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{
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uint16_t offset1;
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uint16_t selector;
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uint8_t IST;
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uint8_t flags;
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uint16_t offset2;
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uint32_t offset3;
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uint32_t reserved;
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} __attribute__((packed));
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struct IDTR
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{
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uint16_t size;
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uint64_t offset;
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} __attribute__((packed));
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static IDTR s_idtr;
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static GateDescriptor* s_idt = nullptr;
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static void(*s_irq_handlers[0x10])() { nullptr };
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static const char* isr_exceptions[] =
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{
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"Division Error",
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"Debug",
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"Non-maskable Interrupt",
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"Breakpoint",
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"Overflow",
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"Bound Range Exception",
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"Invalid Opcode",
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"Device Not Available",
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"Double Fault",
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"Coprocessor Segment Overrun",
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"Invalid TSS",
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"Segment Not Present",
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"Stack-Segment Fault",
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"General Protection Fault",
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"Page Fault",
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"Unknown Exception 0x0F",
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"x87 Floating-Point Exception",
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"Alignment Check",
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"Machine Check",
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"SIMD Floating-Point Exception",
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"Virtualization Exception",
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"Control Protection Exception",
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"Unknown Exception 0x16",
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"Unknown Exception 0x17",
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"Unknown Exception 0x18",
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"Unknown Exception 0x19",
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"Unknown Exception 0x1A",
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"Unknown Exception 0x1B",
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"Hypervisor Injection Exception",
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"VMM Communication Exception",
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"Security Exception",
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"Unkown Exception 0x1F",
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};
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extern "C" void cpp_isr_handler(uint64_t isr, uint64_t error, const Registers* regs)
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{
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Kernel::panic(
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"{} (error code: 0x{16H})\r\n"
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"Register dump\r\n"
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"rax=0x{16H}, rbx=0x{16H}, rcx=0x{16H}, rdx=0x{16H}\r\n"
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"rsp=0x{16H}, rbp=0x{16H}, rdi=0x{16H}, rsi=0x{16H}\r\n"
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"rip=0x{16H}, rflags=0x{16H}\r\n"
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"cr0=0x{16H}, cr2=0x{16H}, cr3=0x{16H}, cr4=0x{16H}\r\n",
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isr_exceptions[isr], error,
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regs->rax, regs->rbx, regs->rcx, regs->rdx,
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regs->rsp, regs->rbp, regs->rdi, regs->rsi,
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regs->rip, regs->rflags,
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regs->cr0, regs->cr2, regs->cr3, regs->cr4
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);
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}
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extern "C" void cpp_irq_handler(uint64_t irq)
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{
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if (s_irq_handlers[irq])
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s_irq_handlers[irq]();
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else
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{
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if (!InterruptController::get().is_in_service(irq))
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{
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dprintln("spurious irq 0x{2H}", irq);
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return;
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}
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dprintln("no handler for irq 0x{2H}\n", irq);
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}
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// NOTE: Scheduler sends PIT eoi's
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if (irq != PIT_IRQ)
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InterruptController::get().eoi(irq);
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}
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static void flush_idt()
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{
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asm volatile("lidt %0"::"m"(s_idtr));
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}
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static void register_interrupt_handler(uint8_t index, void(*handler)())
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{
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GateDescriptor& descriptor = s_idt[index];
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descriptor.offset1 = (uint16_t)((uint64_t)handler >> 0);
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descriptor.offset2 = (uint16_t)((uint64_t)handler >> 16);
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descriptor.offset3 = (uint32_t)((uint64_t)handler >> 32);
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descriptor.selector = 0x08;
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descriptor.IST = 0;
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descriptor.flags = 0x8E;
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}
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void register_irq_handler(uint8_t irq, void(*handler)())
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{
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s_irq_handlers[irq] = handler;
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}
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extern "C" void isr0();
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extern "C" void isr1();
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extern "C" void isr2();
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extern "C" void isr3();
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extern "C" void isr4();
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extern "C" void isr5();
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extern "C" void isr6();
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extern "C" void isr7();
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extern "C" void isr8();
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extern "C" void isr9();
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extern "C" void isr10();
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extern "C" void isr11();
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extern "C" void isr12();
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extern "C" void isr13();
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extern "C" void isr14();
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extern "C" void isr15();
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extern "C" void isr16();
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extern "C" void isr17();
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extern "C" void isr18();
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extern "C" void isr19();
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extern "C" void isr20();
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extern "C" void isr21();
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extern "C" void isr22();
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extern "C" void isr23();
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extern "C" void isr24();
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extern "C" void isr25();
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extern "C" void isr26();
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extern "C" void isr27();
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extern "C" void isr28();
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extern "C" void isr29();
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extern "C" void isr30();
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extern "C" void isr31();
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extern "C" void irq0();
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extern "C" void irq1();
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extern "C" void irq2();
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extern "C" void irq3();
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extern "C" void irq4();
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extern "C" void irq5();
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extern "C" void irq6();
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extern "C" void irq7();
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extern "C" void irq8();
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extern "C" void irq9();
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extern "C" void irq10();
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extern "C" void irq11();
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extern "C" void irq12();
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extern "C" void irq13();
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extern "C" void irq14();
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extern "C" void irq15();
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void initialize()
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{
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s_idt = (GateDescriptor*)kmalloc(0x100 * sizeof(GateDescriptor));
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ASSERT(s_idt);
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memset(s_idt, 0x00, 0x100 * sizeof(GateDescriptor));
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s_idtr.offset = (uint64_t)s_idt;
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s_idtr.size = 0x100 * sizeof(GateDescriptor) - 1;
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REGISTER_ISR_HANDLER(0);
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REGISTER_ISR_HANDLER(1);
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REGISTER_ISR_HANDLER(2);
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REGISTER_ISR_HANDLER(3);
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REGISTER_ISR_HANDLER(4);
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REGISTER_ISR_HANDLER(5);
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REGISTER_ISR_HANDLER(6);
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REGISTER_ISR_HANDLER(7);
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REGISTER_ISR_HANDLER(8);
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REGISTER_ISR_HANDLER(9);
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REGISTER_ISR_HANDLER(10);
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REGISTER_ISR_HANDLER(11);
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REGISTER_ISR_HANDLER(12);
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REGISTER_ISR_HANDLER(13);
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REGISTER_ISR_HANDLER(14);
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REGISTER_ISR_HANDLER(15);
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REGISTER_ISR_HANDLER(16);
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REGISTER_ISR_HANDLER(17);
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REGISTER_ISR_HANDLER(18);
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REGISTER_ISR_HANDLER(19);
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REGISTER_ISR_HANDLER(20);
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REGISTER_ISR_HANDLER(21);
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REGISTER_ISR_HANDLER(22);
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REGISTER_ISR_HANDLER(23);
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REGISTER_ISR_HANDLER(24);
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REGISTER_ISR_HANDLER(25);
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REGISTER_ISR_HANDLER(26);
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REGISTER_ISR_HANDLER(27);
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REGISTER_ISR_HANDLER(28);
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REGISTER_ISR_HANDLER(29);
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REGISTER_ISR_HANDLER(30);
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REGISTER_ISR_HANDLER(31);
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REGISTER_IRQ_HANDLER(0);
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REGISTER_IRQ_HANDLER(1);
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REGISTER_IRQ_HANDLER(2);
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REGISTER_IRQ_HANDLER(3);
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REGISTER_IRQ_HANDLER(4);
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REGISTER_IRQ_HANDLER(5);
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REGISTER_IRQ_HANDLER(6);
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REGISTER_IRQ_HANDLER(7);
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REGISTER_IRQ_HANDLER(8);
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REGISTER_IRQ_HANDLER(9);
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REGISTER_IRQ_HANDLER(10);
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REGISTER_IRQ_HANDLER(11);
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REGISTER_IRQ_HANDLER(12);
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REGISTER_IRQ_HANDLER(13);
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REGISTER_IRQ_HANDLER(14);
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REGISTER_IRQ_HANDLER(15);
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flush_idt();
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}
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} |