From 7f029b271305f2ed5ee01015cb300b794cda0919 Mon Sep 17 00:00:00 2001
From: Bananymous <oskari.alaranta@bananymous.com>
Date: Fri, 22 Mar 2024 13:33:13 +0200
Subject: [PATCH] Kernel: Allow Processor compilation for i386 targets

This is achieved by rewriting some inline assembly and changing
ProcessorID to be 32 bit value. For some reason if processor id
is 8 bits gcc runs out of 8 bit registers on i386.
---
 kernel/include/kernel/Processor.h | 26 +++++++++++++-------------
 kernel/kernel/Processor.cpp       | 11 ++++++-----
 2 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/kernel/include/kernel/Processor.h b/kernel/include/kernel/Processor.h
index fe039349a2..f559f308d0 100644
--- a/kernel/include/kernel/Processor.h
+++ b/kernel/include/kernel/Processor.h
@@ -16,10 +16,10 @@ namespace Kernel
 		Enabled,
 	};
 
-	using ProcessorID = uint8_t;
-	constexpr ProcessorID PROCESSOR_NONE = 0xFF;
+	using ProcessorID = uint32_t;
+	constexpr ProcessorID PROCESSOR_NONE = 0xFFFFFFFF;
 
-#if ARCH(x86_64)
+#if ARCH(x86_64) || ARCH(i386)
 	class Processor
 	{
 		BAN_NON_COPYABLE(Processor);
@@ -75,16 +75,16 @@ namespace Kernel
 		template<typename T>
 		static T read_gs_sized(uintptr_t offset) requires(sizeof(T) <= 8)
 		{
-#define __ASM_INPUT(operation) operation " %%gs:%a[offset], %[result]" : [result]"=r"(result) : [offset]"ir"(offset)
+#define __ASM_INPUT(operation) asm volatile(operation " %%gs:%a[offset], %[result]" : [result]"=r"(result) : [offset]"ir"(offset))
 			T result;
 			if constexpr(sizeof(T) == 8)
-				asm volatile(__ASM_INPUT("movq"));
+				__ASM_INPUT("movq");
 			if constexpr(sizeof(T) == 4)
-				asm volatile(__ASM_INPUT("movl"));
+				__ASM_INPUT("movl");
 			if constexpr(sizeof(T) == 2)
-				asm volatile(__ASM_INPUT("movw"));
+				__ASM_INPUT("movw");
 			if constexpr(sizeof(T) == 1)
-				asm volatile(__ASM_INPUT("movb"));
+				__ASM_INPUT("movb");
 			return result;
 #undef __ASM_INPUT
 		}
@@ -92,15 +92,15 @@ namespace Kernel
 		template<typename T>
 		static void write_gs_sized(uintptr_t offset, T value) requires(sizeof(T) <= 8)
 		{
-#define __ASM_INPUT(operation) operation " %[value], %%gs:%a[offset]" :: [value]"r"(value), [offset]"ir"(offset) : "memory"
+#define __ASM_INPUT(operation) asm volatile(operation " %[value], %%gs:%a[offset]" :: [value]"r"(value), [offset]"ir"(offset) : "memory")
 			if constexpr(sizeof(T) == 8)
-				asm volatile(__ASM_INPUT("movq"));
+				__ASM_INPUT("movq");
 			if constexpr(sizeof(T) == 4)
-				asm volatile(__ASM_INPUT("movl"));
+				__ASM_INPUT("movl");
 			if constexpr(sizeof(T) == 2)
-				asm volatile(__ASM_INPUT("movw"));
+				__ASM_INPUT("movw");
 			if constexpr(sizeof(T) == 1)
-				asm volatile(__ASM_INPUT("movb"));
+				__ASM_INPUT("movb");
 #undef __ASM_INPUT
 		}
 
diff --git a/kernel/kernel/Processor.cpp b/kernel/kernel/Processor.cpp
index f7805f9f83..a9b6acd819 100644
--- a/kernel/kernel/Processor.cpp
+++ b/kernel/kernel/Processor.cpp
@@ -13,14 +13,13 @@ namespace Kernel
 
 	static ProcessorID read_processor_id()
 	{
-		uint8_t id;
+		uint32_t id;
 		asm volatile(
 			"movl $1, %%eax;"
 			"cpuid;"
 			"shrl $24, %%ebx;"
-			"movb %%bl, %0;"
-			: "=rm"(id)
-			:: "eax", "ebx", "ecx", "edx"
+			: "=b"(id)
+			:: "eax", "ecx", "edx"
 		);
 		return id;
 	}
@@ -55,7 +54,9 @@ namespace Kernel
 
 		// set gs base to pointer to this processor
 		uint64_t ptr = reinterpret_cast<uint64_t>(&processor);
-		asm volatile("wrmsr" :: "d"(ptr >> 32), "a"(ptr), "c"(MSR_IA32_GS_BASE));
+		uint32_t ptr_hi = ptr >> 32;
+		uint32_t ptr_lo = ptr & 0xFFFFFFFF;
+		asm volatile("wrmsr" :: "d"(ptr_hi), "a"(ptr_lo), "c"(MSR_IA32_GS_BASE));
 
 		ASSERT(processor.m_gdt);
 		processor.gdt().load();