forked from Bananymous/banan-os
Kernel: PCI devices can now create region for BAR
This creates either MEM or IO region for read/write access to PCI device.
This commit is contained in:
Bananymous
parent
14a608effd
commit
7774f56ab6
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@ -13,7 +13,7 @@ namespace Kernel
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class E1000 final : public NetworkDriver
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{
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public:
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static BAN::ErrorOr<BAN::UniqPtr<E1000>> create(const PCIDevice&);
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static BAN::ErrorOr<BAN::UniqPtr<E1000>> create(PCI::Device&);
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~E1000();
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virtual uint8_t* get_mac_address() override { return m_mac_address; }
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@ -24,12 +24,12 @@ namespace Kernel
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private:
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E1000() = default;
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BAN::ErrorOr<void> initialize(const PCIDevice&);
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BAN::ErrorOr<void> initialize(PCI::Device&);
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static void interrupt_handler();
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void write32(uint16_t reg, uint32_t value);
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uint32_t read32(uint16_t reg);
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void write32(uint16_t reg, uint32_t value);
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void detect_eeprom();
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uint32_t eeprom_read(uint8_t addr);
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@ -44,8 +44,7 @@ namespace Kernel
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void handle_receive();
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private:
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PCIDevice::BarType m_bar_type {};
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uint64_t m_bar_addr {};
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BAN::UniqPtr<PCI::BarRegion> m_bar_region;
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bool m_has_eerprom { false };
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uint8_t m_mac_address[6] {};
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uint16_t m_rx_current {};
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@ -1,28 +1,63 @@
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#pragma once
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#include <BAN/UniqPtr.h>
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#include <BAN/Vector.h>
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#include <kernel/Memory/Types.h>
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namespace Kernel
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namespace Kernel::PCI
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{
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class PCIDevice
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enum class BarType
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{
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public:
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enum class BarType
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{
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INVAL,
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MEM,
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IO,
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};
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INVALID,
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MEM,
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IO,
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};
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class Device;
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class BarRegion
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{
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BAN_NON_COPYABLE(BarRegion);
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public:
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PCIDevice(uint8_t, uint8_t, uint8_t);
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static BAN::ErrorOr<BAN::UniqPtr<BarRegion>> create(PCI::Device&, uint8_t bar_num);
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~BarRegion();
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BarType type() const { return m_type; }
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vaddr_t vaddr() const { return m_vaddr; }
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paddr_t paddr() const { return m_paddr; }
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size_t size() const { return m_size; }
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void write8(off_t, uint8_t);
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void write16(off_t, uint16_t);
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void write32(off_t, uint32_t);
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uint8_t read8(off_t);
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uint16_t read16(off_t);
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uint32_t read32(off_t);
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private:
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BarRegion(BarType, paddr_t, size_t);
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BAN::ErrorOr<void> initialize();
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private:
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const BarType m_type {};
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const paddr_t m_paddr {};
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const size_t m_size {};
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vaddr_t m_vaddr {};
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};
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class Device
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{
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public:
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Device(uint8_t, uint8_t, uint8_t);
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uint32_t read_dword(uint8_t) const;
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uint16_t read_word(uint8_t) const;
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uint8_t read_byte(uint8_t) const;
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void write_dword(uint8_t, uint32_t) const;
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void write_dword(uint8_t, uint32_t);
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uint8_t bus() const { return m_bus; }
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uint8_t dev() const { return m_dev; }
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@ -32,17 +67,24 @@ namespace Kernel
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uint8_t subclass() const { return m_subclass; }
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uint8_t prog_if() const { return m_prog_if; }
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BarType read_bar_type(uint8_t) const;
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uint64_t read_bar_address(uint8_t) const;
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uint8_t header_type() const { return m_header_type; }
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void enable_bus_mastering() const;
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void disable_bus_mastering() const;
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BAN::ErrorOr<BAN::UniqPtr<BarRegion>> allocate_bar_region(uint8_t bar_num);
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void enable_memory_space() const;
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void disable_memory_space() const;
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void enable_bus_mastering();
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void disable_bus_mastering();
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void enable_pin_interrupts() const;
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void disable_pin_interrupts() const;
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void enable_memory_space();
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void disable_memory_space();
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void enable_io_space();
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void disable_io_space();
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void enable_pin_interrupts();
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void disable_pin_interrupts();
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private:
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void enumerate_capabilites();
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private:
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uint8_t m_bus;
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@ -56,19 +98,19 @@ namespace Kernel
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uint8_t m_header_type;
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};
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class PCI
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class PCIManager
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{
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BAN_NON_COPYABLE(PCI);
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BAN_NON_MOVABLE(PCI);
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BAN_NON_COPYABLE(PCIManager);
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BAN_NON_MOVABLE(PCIManager);
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public:
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static void initialize();
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static PCI& get();
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static PCIManager& get();
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const BAN::Vector<PCIDevice>& devices() const { return m_devices; }
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const BAN::Vector<PCI::Device>& devices() const { return m_devices; }
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private:
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PCI() = default;
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PCIManager() = default;
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void check_function(uint8_t bus, uint8_t dev, uint8_t func);
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void check_device(uint8_t bus, uint8_t dev);
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void check_bus(uint8_t bus);
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@ -76,7 +118,7 @@ namespace Kernel
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void initialize_devices();
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private:
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BAN::Vector<PCIDevice> m_devices;
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BAN::Vector<PCI::Device> m_devices;
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};
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}
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@ -11,13 +11,13 @@ namespace Kernel
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class ATAController final : public StorageController
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{
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public:
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static BAN::ErrorOr<BAN::RefPtr<ATAController>> create(const PCIDevice&);
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static BAN::ErrorOr<BAN::RefPtr<ATAController>> create(const PCI::Device&);
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virtual BAN::Vector<BAN::RefPtr<StorageDevice>> devices() override;
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private:
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ATAController();
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BAN::ErrorOr<void> initialize(const PCIDevice& device);
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BAN::ErrorOr<void> initialize(const PCI::Device& device);
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private:
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ATABus* m_buses[2] { nullptr, nullptr };
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@ -5,7 +5,7 @@
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#include <kernel/MMIO.h>
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#include <kernel/Networking/E1000.h>
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#define E1000_GENERAL_MEM_SIZE (128 * 1024)
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#define DEBUG_E1000 1
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#define E1000_REG_CTRL 0x0000
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#define E1000_REG_STATUS 0x0008
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@ -112,7 +112,7 @@ namespace Kernel
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volatile uint16_t special;
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} __attribute__((packed));
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BAN::ErrorOr<BAN::UniqPtr<E1000>> E1000::create(const PCIDevice& pci_device)
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BAN::ErrorOr<BAN::UniqPtr<E1000>> E1000::create(PCI::Device& pci_device)
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{
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E1000* e1000 = new E1000();
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ASSERT(e1000);
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@ -126,42 +126,26 @@ namespace Kernel
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E1000::~E1000()
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{
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if (m_bar_type == PCIDevice::BarType::MEM && m_bar_addr)
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PageTable::kernel().unmap_range(m_bar_addr & PAGE_ADDR_MASK, E1000_GENERAL_MEM_SIZE);
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}
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BAN::ErrorOr<void> E1000::initialize(const PCIDevice& pci_device)
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BAN::ErrorOr<void> E1000::initialize(PCI::Device& pci_device)
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{
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m_bar_type = pci_device.read_bar_type(0);
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if (m_bar_type == PCIDevice::BarType::INVAL)
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{
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dwarnln("invalid bar0 type");
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return BAN::Error::from_errno(EINVAL);
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}
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if (m_bar_type == PCIDevice::BarType::MEM)
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{
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uint64_t bar_addr = pci_device.read_bar_address(0);
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vaddr_t page_vaddr = PageTable::kernel().reserve_free_contiguous_pages(E1000_GENERAL_MEM_SIZE / PAGE_SIZE, KERNEL_OFFSET);
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paddr_t page_paddr = bar_addr & PAGE_ADDR_MASK;
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PageTable::kernel().map_range_at(page_paddr, page_vaddr, E1000_GENERAL_MEM_SIZE, PageTable::Flags::CacheDisable | PageTable::Flags::ReadWrite | PageTable::Flags::Present);
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m_bar_addr = page_vaddr + (bar_addr % PAGE_SIZE);
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}
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else if (m_bar_type == PCIDevice::BarType::IO)
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{
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m_bar_addr = pci_device.read_bar_address(0);
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}
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m_bar_region = TRY(pci_device.allocate_bar_region(0));
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pci_device.enable_bus_mastering();
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detect_eeprom();
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TRY(read_mac_address());
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dprintln("E1000 at PCI {}:{}.{}", pci_device.bus(), pci_device.dev(), pci_device.func());
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initialize_rx();
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initialize_tx();
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enable_link();
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enable_interrupts();
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#if DEBUG_E1000
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dprintln("E1000 at PCI {}:{}.{}", pci_device.bus(), pci_device.dev(), pci_device.func());
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dprintln(" MAC: {2H}:{2H}:{2H}:{2H}:{2H}:{2H}",
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m_mac_address[0],
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m_mac_address[1],
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@ -170,52 +154,22 @@ namespace Kernel
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m_mac_address[4],
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m_mac_address[5]
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);
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initialize_rx();
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initialize_tx();
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enable_link();
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enable_interrupts();
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dprintln(" link up: {}", link_up());
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if (link_up())
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dprintln(" link speed: {} Mbps", link_speed());
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#endif
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return {};
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}
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void E1000::write32(uint16_t reg, uint32_t value)
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{
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switch (m_bar_type)
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{
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case PCIDevice::BarType::MEM:
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MMIO::write32(m_bar_addr + reg, value);
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break;
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case PCIDevice::BarType::IO:
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IO::outl(m_bar_addr, reg);
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IO::outl(m_bar_addr + 4, value);
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break;
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default:
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ASSERT_NOT_REACHED();
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}
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m_bar_region->write32(reg, value);
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}
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uint32_t E1000::read32(uint16_t reg)
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{
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uint32_t result = 0;
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switch (m_bar_type)
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{
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case PCIDevice::BarType::MEM:
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result = MMIO::read32(m_bar_addr + reg);
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break;
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case PCIDevice::BarType::IO:
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IO::outl(m_bar_addr, reg);
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result = IO::inl(m_bar_addr + 4);
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break;
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default:
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ASSERT_NOT_REACHED();
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}
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return result;
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return m_bar_region->read32(reg);
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}
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void E1000::detect_eeprom()
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@ -1,33 +1,22 @@
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#include <kernel/IO.h>
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#include <kernel/Memory/PageTable.h>
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#include <kernel/MMIO.h>
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#include <kernel/Networking/E1000.h>
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#include <kernel/PCI.h>
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#include <kernel/Storage/ATAController.h>
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#define INVALID 0xFFFF
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#define INVALID_VENDOR 0xFFFF
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#define MULTI_FUNCTION 0x80
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#define CONFIG_ADDRESS 0xCF8
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#define CONFIG_DATA 0xCFC
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namespace Kernel
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#define DEBUG_PCI 1
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namespace Kernel::PCI
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{
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static PCI* s_instance = nullptr;
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void PCI::initialize()
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{
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ASSERT(s_instance == nullptr);
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s_instance = new PCI();
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ASSERT(s_instance);
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s_instance->check_all_buses();
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s_instance->initialize_devices();
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}
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PCI& PCI::get()
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{
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ASSERT(s_instance);
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return *s_instance;
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}
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static PCIManager* s_instance = nullptr;
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static uint32_t read_config_dword(uint8_t bus, uint8_t dev, uint8_t func, uint8_t offset)
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{
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@ -55,7 +44,22 @@ namespace Kernel
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return (dword >> 16) & 0xFF;
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}
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void PCI::check_function(uint8_t bus, uint8_t dev, uint8_t func)
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void PCIManager::initialize()
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{
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ASSERT(s_instance == nullptr);
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s_instance = new PCIManager();
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ASSERT(s_instance);
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s_instance->check_all_buses();
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s_instance->initialize_devices();
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}
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PCIManager& PCIManager::get()
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{
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ASSERT(s_instance);
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return *s_instance;
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}
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void PCIManager::check_function(uint8_t bus, uint8_t dev, uint8_t func)
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{
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MUST(m_devices.emplace_back(bus, dev, func));
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auto& device = m_devices.back();
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@ -63,29 +67,29 @@ namespace Kernel
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check_bus(device.read_byte(0x19));
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}
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void PCI::check_device(uint8_t bus, uint8_t dev)
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void PCIManager::check_device(uint8_t bus, uint8_t dev)
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{
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if (get_vendor_id(bus, dev, 0) == INVALID)
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if (get_vendor_id(bus, dev, 0) == INVALID_VENDOR)
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return;
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check_function(bus, dev, 0);
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if (get_header_type(bus, dev, 0) & MULTI_FUNCTION)
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for (uint8_t func = 1; func < 8; func++)
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if (get_vendor_id(bus, dev, func) != INVALID)
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if (get_vendor_id(bus, dev, func) != INVALID_VENDOR)
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check_function(bus, dev, func);
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}
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void PCI::check_bus(uint8_t bus)
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void PCIManager::check_bus(uint8_t bus)
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{
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for (uint8_t dev = 0; dev < 32; dev++)
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check_device(bus, dev);
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}
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void PCI::check_all_buses()
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void PCIManager::check_all_buses()
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{
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if (get_header_type(0, 0, 0) & MULTI_FUNCTION)
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{
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for (int func = 0; func < 8 && get_vendor_id(0, 0, func) != INVALID; func++)
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for (int func = 0; func < 8 && get_vendor_id(0, 0, func) != INVALID_VENDOR; func++)
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check_bus(func);
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}
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else
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@ -94,9 +98,9 @@ namespace Kernel
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}
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}
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void PCI::initialize_devices()
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void PCIManager::initialize_devices()
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{
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for (const auto& pci_device : PCI::get().devices())
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for (auto& pci_device : m_devices)
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{
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switch (pci_device.class_code())
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{
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@ -134,7 +138,144 @@ namespace Kernel
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}
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}
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PCIDevice::PCIDevice(uint8_t bus, uint8_t dev, uint8_t func)
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BAN::ErrorOr<BAN::UniqPtr<BarRegion>> BarRegion::create(PCI::Device& device, uint8_t bar_num)
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{
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ASSERT(device.header_type() == 0x00);
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uint32_t command_status = device.read_dword(0x04);
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// disable io/mem space while reading bar
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device.write_dword(0x04, command_status & ~3);
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uint8_t offset = 0x10 + bar_num * 8;
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uint64_t addr = device.read_dword(offset);
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device.write_dword(offset, 0xFFFFFFFF);
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uint32_t size = device.read_dword(0x10 + bar_num * 8);
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size = ~size + 1;
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device.write_dword(offset, addr);
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// determine bar type
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BarType type = BarType::INVALID;
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if (addr & 1)
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{
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type = BarType::IO;
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addr &= 0xFFFFFFFC;
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}
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else if ((addr & 0b110) == 0b000)
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{
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type = BarType::MEM;
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addr &= 0xFFFFFFF0;
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}
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else if ((addr & 0b110) == 0b100)
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{
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type = BarType::MEM;
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addr &= 0xFFFFFFF0;
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addr |= (uint64_t)device.read_dword(offset + 8) << 32;
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}
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if (type == BarType::INVALID)
|
||||
{
|
||||
dwarnln("invalid pci device bar");
|
||||
return BAN::Error::from_errno(EINVAL);
|
||||
}
|
||||
|
||||
auto* region_ptr = new BarRegion(type, addr, size);
|
||||
ASSERT(region_ptr);
|
||||
|
||||
auto region = BAN::UniqPtr<BarRegion>::adopt(region_ptr);
|
||||
TRY(region->initialize());
|
||||
|
||||
// restore old command register and enable correct IO/MEM
|
||||
command_status |= (type == BarType::IO) ? 1 : 2;
|
||||
device.write_dword(0x04, command_status);
|
||||
|
||||
#if DEBUG_PCI
|
||||
dprintln("created BAR region for PCI {}:{}.{}",
|
||||
device.bus(),
|
||||
device.dev(),
|
||||
device.func()
|
||||
);
|
||||
dprintln(" type: {}", region->type() == BarType::IO ? "IO" : "MEM");
|
||||
dprintln(" paddr {}", (void*)region->paddr());
|
||||
dprintln(" vaddr {}", (void*)region->vaddr());
|
||||
dprintln(" size {}", region->size());
|
||||
#endif
|
||||
|
||||
return region;
|
||||
}
|
||||
|
||||
BarRegion::BarRegion(BarType type, paddr_t paddr, size_t size)
|
||||
: m_type(type)
|
||||
, m_paddr(paddr)
|
||||
, m_size(size)
|
||||
{ }
|
||||
|
||||
BarRegion::~BarRegion()
|
||||
{
|
||||
if (m_type == BarType::MEM && m_vaddr)
|
||||
PageTable::kernel().unmap_range(m_vaddr, m_size);
|
||||
m_vaddr = 0;
|
||||
}
|
||||
|
||||
BAN::ErrorOr<void> BarRegion::initialize()
|
||||
{
|
||||
if (m_type == BarType::IO)
|
||||
return {};
|
||||
|
||||
size_t needed_pages = BAN::Math::div_round_up<size_t>(m_size, PAGE_SIZE);
|
||||
m_vaddr = PageTable::kernel().reserve_free_contiguous_pages(needed_pages, KERNEL_OFFSET);
|
||||
if (m_vaddr == 0)
|
||||
return BAN::Error::from_errno(ENOMEM);
|
||||
PageTable::kernel().map_range_at(m_paddr, m_vaddr, m_size, PageTable::Flags::CacheDisable | PageTable::Flags::ReadWrite | PageTable::Flags::Present);
|
||||
|
||||
return {};
|
||||
}
|
||||
|
||||
void BarRegion::write8(off_t reg, uint8_t val)
|
||||
{
|
||||
if (m_type == BarType::IO)
|
||||
return IO::outb(m_vaddr + reg, val);
|
||||
MMIO::write8(m_vaddr + reg, val);
|
||||
}
|
||||
|
||||
void BarRegion::write16(off_t reg, uint16_t val)
|
||||
{
|
||||
if (m_type == BarType::IO)
|
||||
return IO::outw(m_vaddr + reg, val);
|
||||
MMIO::write16(m_vaddr + reg, val);
|
||||
}
|
||||
|
||||
void BarRegion::write32(off_t reg, uint32_t val)
|
||||
{
|
||||
if (m_type == BarType::IO)
|
||||
return IO::outl(m_vaddr + reg, val);
|
||||
MMIO::write32(m_vaddr + reg, val);
|
||||
}
|
||||
|
||||
uint8_t BarRegion::read8(off_t reg)
|
||||
{
|
||||
if (m_type == BarType::IO)
|
||||
return IO::inb(m_vaddr + reg);
|
||||
return MMIO::read8(m_vaddr + reg);
|
||||
}
|
||||
|
||||
uint16_t BarRegion::read16(off_t reg)
|
||||
{
|
||||
if (m_type == BarType::IO)
|
||||
return IO::inw(m_vaddr + reg);
|
||||
return MMIO::read16(m_vaddr + reg);
|
||||
}
|
||||
|
||||
uint32_t BarRegion::read32(off_t reg)
|
||||
{
|
||||
if (m_type == BarType::IO)
|
||||
return IO::inl(m_vaddr + reg);
|
||||
return MMIO::read32(m_vaddr + reg);
|
||||
}
|
||||
|
||||
PCI::Device::Device(uint8_t bus, uint8_t dev, uint8_t func)
|
||||
: m_bus(bus), m_dev(dev), m_func(func)
|
||||
{
|
||||
uint32_t type = read_word(0x0A);
|
||||
|
|
@ -142,87 +283,92 @@ namespace Kernel
|
|||
m_subclass = (uint8_t)(type);
|
||||
m_prog_if = read_byte(0x09);
|
||||
m_header_type = read_byte(0x0E);
|
||||
|
||||
enumerate_capabilites();
|
||||
}
|
||||
|
||||
uint32_t PCIDevice::read_dword(uint8_t offset) const
|
||||
uint32_t PCI::Device::read_dword(uint8_t offset) const
|
||||
{
|
||||
ASSERT((offset & 0x03) == 0);
|
||||
return read_config_dword(m_bus, m_dev, m_func, offset);
|
||||
}
|
||||
|
||||
uint16_t PCIDevice::read_word(uint8_t offset) const
|
||||
uint16_t PCI::Device::read_word(uint8_t offset) const
|
||||
{
|
||||
ASSERT((offset & 0x01) == 0);
|
||||
uint32_t dword = read_config_dword(m_bus, m_dev, m_func, offset & 0xFC);
|
||||
return (uint16_t)(dword >> (8 * (offset & 0x03)));
|
||||
}
|
||||
|
||||
uint8_t PCIDevice::read_byte(uint8_t offset) const
|
||||
uint8_t PCI::Device::read_byte(uint8_t offset) const
|
||||
{
|
||||
uint32_t dword = read_config_dword(m_bus, m_dev, m_func, offset & 0xFC);
|
||||
return (uint8_t)(dword >> (8 * (offset & 0x03)));
|
||||
}
|
||||
|
||||
void PCIDevice::write_dword(uint8_t offset, uint32_t value) const
|
||||
void PCI::Device::write_dword(uint8_t offset, uint32_t value)
|
||||
{
|
||||
ASSERT((offset & 0x03) == 0);
|
||||
write_config_dword(m_bus, m_dev, m_func, offset, value);
|
||||
}
|
||||
|
||||
PCIDevice::BarType PCIDevice::read_bar_type(uint8_t bar) const
|
||||
BAN::ErrorOr<BAN::UniqPtr<BarRegion>> PCI::Device::allocate_bar_region(uint8_t bar_num)
|
||||
{
|
||||
ASSERT(m_header_type == 0x00);
|
||||
ASSERT(bar <= 5);
|
||||
|
||||
uint32_t type = read_dword(0x10 + bar * 4) & 0b111;
|
||||
if (type & 1)
|
||||
return BarType::IO;
|
||||
type >>= 1;
|
||||
if (type == 0x0 || type == 0x2)
|
||||
return BarType::MEM;
|
||||
return BarType::INVAL;
|
||||
return BarRegion::create(*this, bar_num);
|
||||
}
|
||||
|
||||
uint64_t PCIDevice::read_bar_address(uint8_t bar) const
|
||||
void PCI::Device::enumerate_capabilites()
|
||||
{
|
||||
ASSERT(m_header_type == 0x00);
|
||||
ASSERT(bar <= 5);
|
||||
uint16_t status = read_word(0x06);
|
||||
if (!(status & (1 << 4)))
|
||||
return;
|
||||
|
||||
uint64_t address = read_dword(0x10 + bar * 4);
|
||||
if (address & 1)
|
||||
return address & 0xFFFFFFFC;
|
||||
if ((address & 0b110) == 0b100)
|
||||
address |= (uint64_t)read_dword(0x10 + bar * 4 + 4) << 32;
|
||||
return address & 0xFFFFFFFFFFFFFFF0;
|
||||
uint8_t capabilities = read_byte(0x34) & 0xFC;
|
||||
while (capabilities)
|
||||
{
|
||||
uint16_t next = read_word(capabilities);
|
||||
dprintln(" cap {2H}", next & 0xFF);
|
||||
capabilities = (next >> 8) & 0xFC;
|
||||
}
|
||||
}
|
||||
|
||||
void PCIDevice::enable_bus_mastering() const
|
||||
void PCI::Device::enable_bus_mastering()
|
||||
{
|
||||
write_dword(0x04, read_dword(0x04) | 1u << 2);
|
||||
}
|
||||
|
||||
void PCIDevice::disable_bus_mastering() const
|
||||
void PCI::Device::disable_bus_mastering()
|
||||
{
|
||||
write_dword(0x04, read_dword(0x04) & ~(1u << 2));
|
||||
|
||||
}
|
||||
|
||||
void PCIDevice::enable_memory_space() const
|
||||
void PCI::Device::enable_memory_space()
|
||||
{
|
||||
write_dword(0x04, read_dword(0x04) | 1u << 1);
|
||||
}
|
||||
|
||||
void PCIDevice::disable_memory_space() const
|
||||
void PCI::Device::disable_memory_space()
|
||||
{
|
||||
write_dword(0x04, read_dword(0x04) & ~(1u << 1));
|
||||
}
|
||||
|
||||
void PCIDevice::enable_pin_interrupts() const
|
||||
void PCI::Device::enable_io_space()
|
||||
{
|
||||
write_dword(0x04, read_dword(0x04) | 1u << 0);
|
||||
}
|
||||
|
||||
void PCI::Device::disable_io_space()
|
||||
{
|
||||
write_dword(0x04, read_dword(0x04) & ~(1u << 0));
|
||||
}
|
||||
|
||||
void PCI::Device::enable_pin_interrupts()
|
||||
{
|
||||
write_dword(0x04, read_dword(0x04) | 1u << 10);
|
||||
}
|
||||
|
||||
void PCIDevice::disable_pin_interrupts() const
|
||||
void PCI::Device::disable_pin_interrupts()
|
||||
{
|
||||
write_dword(0x04, read_dword(0x04) & ~(1u << 10));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
namespace Kernel
|
||||
{
|
||||
|
||||
BAN::ErrorOr<BAN::RefPtr<ATAController>> ATAController::create(const PCIDevice& device)
|
||||
BAN::ErrorOr<BAN::RefPtr<ATAController>> ATAController::create(const PCI::Device& device)
|
||||
{
|
||||
ATAController* controller = new ATAController();
|
||||
if (controller == nullptr)
|
||||
|
|
@ -50,7 +50,7 @@ namespace Kernel
|
|||
: m_rdev(makedev(DevFileSystem::get().get_next_dev(), 0))
|
||||
{ }
|
||||
|
||||
BAN::ErrorOr<void> ATAController::initialize(const PCIDevice& pci_device)
|
||||
BAN::ErrorOr<void> ATAController::initialize(const PCI::Device& pci_device)
|
||||
{
|
||||
struct Bus
|
||||
{
|
||||
|
|
|
|||
|
|
@ -167,7 +167,7 @@ static void init2(void*)
|
|||
|
||||
DevFileSystem::get().initialize_device_updater();
|
||||
|
||||
PCI::initialize();
|
||||
PCI::PCIManager::initialize();
|
||||
dprintln("PCI initialized");
|
||||
|
||||
VirtualFileSystem::initialize(cmdline.root);
|
||||
|
|
|
|||
Loading…
Reference in New Issue