2023-03-01 21:21:08 +02:00
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#include <BAN/Assert.h>
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#include <kernel/GDT.h>
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#include <string.h>
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extern "C" uintptr_t g_boot_stack_top[0];
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namespace Kernel::GDT
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{
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struct TaskStateSegment
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{
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uint32_t reserved1;
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uint64_t rsp0;
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uint64_t rsp1;
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uint64_t rsp2;
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uint64_t reserved2;
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uint64_t ist1;
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uint64_t ist2;
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uint64_t ist3;
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uint64_t ist4;
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uint64_t ist5;
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uint64_t ist6;
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uint64_t ist7;
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uint64_t reserved3;
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uint16_t reserved4;
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uint16_t iopb;
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} __attribute__((packed));
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union SegmentDescriptor
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{
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struct
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{
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uint16_t limit1;
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uint16_t base1;
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uint8_t base2;
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uint8_t access;
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uint8_t limit2 : 4;
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uint8_t flags : 4;
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uint8_t base3;
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} __attribute__((packed));
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struct
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{
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uint32_t low;
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uint32_t high;
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} __attribute__((packed));
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} __attribute__((packed));
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struct GDTR
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{
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uint16_t size;
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uint64_t address;
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} __attribute__((packed));
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2023-05-06 00:57:00 +03:00
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static constexpr uint16_t s_tss_offset = 0x28;
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2023-04-25 14:48:12 +03:00
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2023-03-01 21:21:08 +02:00
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static TaskStateSegment* s_tss = nullptr;
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static SegmentDescriptor* s_gdt = nullptr;
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static GDTR s_gdtr;
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static void write_entry(uint8_t offset, uint32_t base, uint32_t limit, uint8_t access, uint8_t flags)
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{
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SegmentDescriptor& desc = *(SegmentDescriptor*)((uintptr_t)s_gdt + offset);
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desc.base1 = base;
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desc.base2 = base >> 16;
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desc.base3 = base >> 24;
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desc.limit1 = limit;
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desc.limit2 = limit >> 16;
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desc.access = access;
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desc.flags = flags;
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}
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2023-04-25 14:48:12 +03:00
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static void write_tss()
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2023-03-01 21:21:08 +02:00
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{
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s_tss = new TaskStateSegment();
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ASSERT(s_tss);
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memset(s_tss, 0x00, sizeof(TaskStateSegment));
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2023-04-25 14:48:12 +03:00
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s_tss->rsp0 = 0;
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2023-03-01 21:21:08 +02:00
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uintptr_t base = (uintptr_t)s_tss;
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2023-04-25 14:48:12 +03:00
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write_entry(s_tss_offset, (uint32_t)base, sizeof(TaskStateSegment), 0x89, 0x0);
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SegmentDescriptor& desc = *(SegmentDescriptor*)((uintptr_t)s_gdt + s_tss_offset + 0x08);
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2023-03-01 21:21:08 +02:00
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desc.low = base >> 32;
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desc.high = 0;
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}
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2023-04-25 14:48:12 +03:00
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void set_tss_stack(uintptr_t rsp)
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{
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s_tss->rsp0 = rsp;
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}
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2023-03-01 21:21:08 +02:00
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static void flush_gdt()
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{
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asm volatile("lgdt %0" :: "m"(s_gdtr));
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}
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2023-04-25 14:48:12 +03:00
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static void flush_tss()
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2023-03-01 21:21:08 +02:00
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{
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2023-04-25 14:48:12 +03:00
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asm volatile("ltr %0" :: "m"(s_tss_offset));
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2023-03-01 21:21:08 +02:00
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}
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void initialize()
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{
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constexpr uint32_t descriptor_count = 6 + 1; // tss takes 2
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s_gdt = new SegmentDescriptor[descriptor_count];
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ASSERT(s_gdt);
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s_gdtr.address = (uint64_t)s_gdt;
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s_gdtr.size = descriptor_count * sizeof(SegmentDescriptor) - 1;
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write_entry(0x00, 0x00000000, 0x00000, 0x00, 0x0); // null
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write_entry(0x08, 0x00000000, 0xFFFFF, 0x9A, 0xA); // kernel code
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write_entry(0x10, 0x00000000, 0xFFFFF, 0x92, 0xC); // kernel data
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write_entry(0x18, 0x00000000, 0xFFFFF, 0xFA, 0xA); // user code
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write_entry(0x20, 0x00000000, 0xFFFFF, 0xF2, 0xC); // user data
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2023-04-25 14:48:12 +03:00
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write_tss();
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2023-03-01 21:21:08 +02:00
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flush_gdt();
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2023-04-25 14:48:12 +03:00
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flush_tss();
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2023-03-01 21:21:08 +02:00
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}
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}
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